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path: root/arch/x86/cpu/ivybridge/cpu.c
AgeCommit message (Expand)AuthorFilesLines
2020-05-19common: Drop log.h from common headerSimon Glass1-0/+1
2020-05-19common: Drop init.h from common headerSimon Glass1-0/+1
2019-12-03common: Move checkcpu() out of common.hSimon Glass1-0/+1
2019-10-08x86: pci: Drop the first parameter in pci_x86_r/w_config()Simon Glass1-2/+1
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
2017-04-05board_f: x86: Use checkcpu() for CPU initSimon Glass1-4/+10
2017-02-06x86: ivybridge: Add more debugging for failuresSimon Glass1-1/+3
2016-08-30x86: Add debugging when cpu_common_init() failsSimon Glass1-1/+3
2016-03-17x86: Move common PCH code into a common placeSimon Glass1-0/+1
2016-03-17x86: Move common CPU code to its own placeSimon Glass1-74/+6
2016-03-17x86: Create a common header for Intel register accessSimon Glass1-0/+1
2016-03-17x86: Move microcode code to a common locationSimon Glass1-1/+1
2016-03-15dm: Use uclass_first_device_err() where it is usefulSimon Glass1-9/+5
2016-01-24x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass1-17/+17
2016-01-24x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass1-36/+3
2016-01-24x86: ivybridge: Do the SATA init before relocationSimon Glass1-0/+3
2016-01-24x86: ivybridge: Move GPIO init to the LPC init() methodSimon Glass1-4/+0
2016-01-24x86: ivybridge: Move graphics init much laterSimon Glass1-1/+0
2016-01-24x86: ivybridge: Probe the LPC in CPU initSimon Glass1-3/+2
2016-01-24x86: ivybridge: Move northbridge init into the probe() methodSimon Glass1-0/+2
2016-01-24x86: ivybridge: Rename bd82x6x_init()Simon Glass1-0/+8
2016-01-24x86: ivybridge: Move more init to the probe() functionSimon Glass1-43/+0
2016-01-24x86: ivybridge: Move lpc_early_init() to probe()Simon Glass1-9/+0
2016-01-24x86: ivybridge: Set up the LPC device using driver modelSimon Glass1-1/+5
2015-12-09x86: Remove HAVE_ACPI_RESUMEBin Meng1-9/+0
2015-12-01x86: Convert to use driver model timerBin Meng1-1/+0
2015-10-21x86: chromebook_link: Enable the debug UARTSimon Glass1-0/+7
2015-04-30x86: ivybridge: Use reset_cpu()Simon Glass1-3/+2
2015-04-18x86: chromebook_link: dts: Add PCH and LPC devicesSimon Glass1-1/+1
2015-04-18dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass1-7/+9
2015-04-17x86: Split up arch_cpu_init()Simon Glass1-0/+8
2015-04-17x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass1-19/+19
2015-01-13x86: ivybridge: Update microcode early in bootSimon Glass1-1/+1
2015-01-13x86: ivybridge: Drop support for ROM cachingSimon Glass1-25/+0
2014-12-14x86: Add post failure codes for bist and carBin Meng1-0/+1
2014-11-21x86: ivybridge: Add LAPIC supportSimon Glass1-0/+3
2014-11-21x86: ivybridge: Add early init for PCH devicesSimon Glass1-0/+141
2014-11-21x86: ivybridge: Perform Intel microcode update on bootSimon Glass1-0/+5
2014-11-21x86: ivybridge: Check BIST value on bootSimon Glass1-0/+16
2014-11-21x86: ivybridge: Perform initial CPU setupSimon Glass1-0/+130
2014-11-21x86: ivybridge: Add early LPC init so that serial worksSimon Glass1-0/+12
2014-11-21x86: ivybridge: Enable PCI in early initSimon Glass1-0/+6
2014-11-21x86: chromebook_link: Implement CAR support (cache as RAM)Simon Glass1-0/+2
2014-11-21x86: Add chromebook_link boardSimon Glass1-0/+42
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