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AgeCommit message (Expand)AuthorFilesLines
2016-03-22arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass1-0/+4
2016-03-17x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese3-0/+283
2016-03-17x86: Add support for the samus chromebookSimon Glass2-0/+629
2016-03-17x86: Support a chained-boot development flowSimon Glass1-0/+80
2016-03-17x86: dts: Drop memory SPD compatible stringSimon Glass1-1/+0
2016-03-17x86: ivybridge: Convert to use the common SDRAM codeSimon Glass1-311/+83
2016-03-17x86: Add common SDRAM-init codeSimon Glass3-0/+327
2016-03-17x86: Move common PCH code into a common placeSimon Glass6-84/+99
2016-03-17x86: Add a function to set the IOAPIC IDSimon Glass2-0/+18
2016-03-17x86: broadwell: Add support for high-speed I/O lane with MESimon Glass2-0/+58
2016-03-17x86: broadwell: Add support for SDRAM setupSimon Glass4-0/+509
2016-03-17x86: broadwell: Add power-control supportSimon Glass3-0/+220
2016-03-17x86: broadwell: Add reference code supportSimon Glass2-0/+114
2016-03-17x86: broadwell: Add an LPC driverSimon Glass3-0/+110
2016-03-17x86: broadwell: Add a northbridge driverSimon Glass2-0/+60
2016-03-17x86: broadwell: Add a SATA driverSimon Glass2-0/+270
2016-03-17x86: broadwell: Add a pinctrl driverSimon Glass3-0/+370
2016-03-17x86: broadwell: Add a PCH driverSimon Glass4-0/+839
2016-03-17x86: Add basic support for broadwellSimon Glass10-0/+1246
2016-03-17x86: Add support for running Intel reference codeSimon Glass2-0/+23
2016-03-17x86: Drop all the old pin configuration codeSimon Glass1-141/+0
2016-03-17x86: Add an ICH6 pin configuration driverSimon Glass3-0/+218
2016-03-17x86: link: Add pin configuration to the device treeSimon Glass1-0/+155
2016-03-17x86: Update microcode for secondary CPUsSimon Glass5-2/+12
2016-03-17x86: ivybridge: Show microcode version for each coreSimon Glass1-1/+2
2016-03-17x86: Record the CPU details when starting each coreSimon Glass3-1/+20
2016-03-17x86: Move common MRC Kconfig options to the common fileSimon Glass2-26/+62
2016-03-17x86: Allow I/O functions to use pointersSimon Glass1-2/+10
2016-03-17x86: Add macros to clear and set I/O bitsSimon Glass1-0/+22
2016-03-17x86: ivybridge: Drop sandybridge_early_init()Simon Glass1-2/+0
2016-03-17x86: Move Intel Management Engine code to a common placeSimon Glass10-369/+418
2016-03-17x86: Rename PORT_RESET to IO_PORT_RESETSimon Glass3-5/+5
2016-03-17x86: Move common CPU code to its own placeSimon Glass6-76/+162
2016-03-17x86: Move common LPC code to its own placeSimon Glass6-85/+166
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass4-7/+9
2016-03-17x86: Create a common header for Intel register accessSimon Glass6-6/+22
2016-03-17x86: Move microcode code to a common locationSimon Glass6-4/+8
2016-03-17x86: Move cache-as-RAM code into a common locationSimon Glass4-1/+8
2016-03-17x86: cpu: Add functions to return the family and steppingSimon Glass2-0/+24
2016-03-17x86: broadwell: Add a few microcode filesSimon Glass2-0/+2272
2016-03-17x86: Add comments to the SIPI vectorSimon Glass2-0/+2
2016-03-17x86: Tidy up mp_init to reduce duplicationSimon Glass1-53/+26
2016-03-17x86: Correct duplicate POST valuesSimon Glass1-2/+2
2016-03-17x86: gpio: Correct GPIO setup orderingSimon Glass1-0/+5
2016-03-17x86: dts: link: Add board ID GPIOsSimon Glass1-0/+2
2016-03-17x86: dts: link: Move SPD info into the memory controllerSimon Glass1-111/+110
2016-03-17x86: link: Add required GPIO propertiesSimon Glass1-3/+9
2016-03-17x86: Add some more common MSR indexesSimon Glass3-20/+43
2016-03-17x86: cpu: Make the vendor table constSimon Glass1-1/+1
2016-03-17x86: Support booting SeaBIOSBin Meng3-0/+28