starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-11-29	clk: starfive: jh7110: Add full i2c clocks	Hal Feng	1	-18/+52
2023-04-23	board: starfive: copyright: Standardize the copyright format	Yanhong Wang	1	-1/+1
2023-02-22	clk: starfive: Add PCIe clocks for PCIe controller	Mason Huo	1	-0/+43
2023-02-17	i2c:desigware-snps: add i2c clock config	keith.zhao	1	-0/+18
2023-01-05	clk:starfive: Add vout clock driver for StarFive JH7110	Yanhong Wang	1	-198/+433
2022-10-18	clk: starfive: jh7110: Modify the parameters of clk_register()	Yan Hong Wang	1	-34/+11
2022-10-18	clk:jh7110: update apb_bus clk relationship	yanhong.wang	1	-26/+7
2022-10-18	clk:jh7110: pll0 dynamically gets the frequency	samin	1	-5/+35
2022-10-18	clk:riscv:starfive: update uart3-uart5 clks	yanhong.wang	1	-16/+24
2022-10-18	clk:starfive-jh7110: Update pll0/pll1/pll2 clk	yanhong.wang	1	-6/+4
2022-10-18	clk:starfive-jh7110: add JH7110_GMAC1_GTXC clk	yanhong.wang	1	-0/+4
2022-10-18	clk:starfive-jh7110: Update pll0/pll1/pll2 clk	yanhong.wang	1	-3/+7
2022-10-18	clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macros	yanhong.wang	1	-2/+2
2022-10-18	clk:starfive-jh7110: remove unused clk	yanhong.wang	1	-52/+4
2022-10-18	clk:starfive-jh7110: Add clock driver for JH7110	yanhong.wang	5	-0/+708
2021-09-17	clk: ti: k3: Update driver to account for divider flags	Suman Anna	1	-2/+2
2021-09-17	clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write	Dave Gerlach	1	-2/+11
2021-08-25	drivers: clk: Add memory clock driver for Intel N5X device	Siew Chin Lim	3	-0/+221
2021-08-25	drivers: clk: Add clock driver for Intel N5X device	Siew Chin Lim	3	-1/+708
2021-08-22	clk: clk_versaclock: Add support for versaclock driver	Adam Ford	3	-0/+1110
2021-08-16	clk: stm32mp1: add support of BSEC clock	Patrick Delaunay	1	-0/+1
2021-08-12	rockchip: px30: Support configure SFC	Jon Lin	1	-0/+32
2021-07-27	clk: stm32mp1: add support of missing SPI clocks	Patrick Delaunay	1	-0/+13
2021-07-26	clk: zynqmp: Add support for enabling clock on lpd_lsbus	Michal Simek	1	-0/+1
2021-07-17	Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u...	Tom Rini	1	-1/+22
2021-07-16	Merge branch '2021-07-15-assorted-fixes'	Tom Rini	1	-1/+5
2021-07-16	clk: stm32mp1: add support of SYSCFG clock	Patrick Delaunay	1	-0/+1
2021-07-16	clk: Detect failure to set defaults	Simon Glass	1	-1/+5
2021-07-14	clk: uniphier: Add PCIe clock entry	Kunihiko Hayashi	1	-0/+3
2021-07-10	clk: imx8mm: Add SPI clocks	Frieder Schrempf	1	-1/+22
2021-07-08	clk: armada-37xx: Set DM_FLAG_PRE_RELOC	Marek Behún	2	-0/+2
2021-07-07	Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm	Tom Rini	1	-0/+2
2021-07-06	dm: define LOG_CATEGORY for all uclass	Patrick Delaunay	1	-0/+2
2021-07-06	drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux'	Green Wan	1	-3/+3
2021-07-01	Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u...	Tom Rini	3	-0/+198
2021-06-29	Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh int...	Tom Rini	7	-0/+371
2021-06-28	Merge tag 'v2021.07-rc5' into next	Tom Rini	1	-2/+6
2021-06-24	clk: renesas: Add R8A779A0 clock tables	Hai Pham	7	-0/+338
2021-06-24	clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code	Marek Vasut	2	-0/+33
2021-06-23	clk: zynq: Add clock wizard driver	Zhengxun	3	-0/+198
2021-06-19	Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodi...	Tom Rini	2	-0/+2960
2021-06-18	clk: cosmetic change in uclass	Patrick Delaunay	1	-1/+1
2021-06-18	rockchip: rk3568: add clock driver	Elaine Zhang	2	-0/+2960
2021-06-17	clk: k210: Move k210 clock out of its own subdirectory	Sean Anderson	5	-15/+14
2021-06-17	clk: k210: Remove bypass driver	Sean Anderson	2	-274/+1
2021-06-17	clk: k210: Don't set PLL rates if we are already at the correct rate	Sean Anderson	1	-7/+8
2021-06-17	clk: k210: Re-add support for setting rate	Sean Anderson	1	-5/+84
2021-06-17	clk: k210: Implement soc_clk_dump	Sean Anderson	1	-2/+66
2021-06-17	clk: k210: Move pll into the rest of the driver	Sean Anderson	3	-594/+601
2021-06-17	clk: k210: Rewrite to remove CCF	Sean Anderson	3	-523/+439