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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
ddr
/
altera
/
sequencer.h
Age
Commit message (
Expand
)
Author
Files
Lines
2020-02-05
ddr: altera: Add DDR2 support to Gen5 driver
Marek Vasut
1
-0
/
+1
2019-07-21
dm: ddr: socfpga: fix gen5 ddr driver to not use bss
Simon Goldschmidt
1
-7
/
+29
2019-04-17
arm: socfpga: move gen5 SDR driver to DM
Simon Goldschmidt
1
-0
/
+35
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2015-08-08
ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
Marek Vasut
1
-45
/
+0
2015-08-08
ddr: altera: sequencer: Zap VFIFO_SIZE
Marek Vasut
1
-3
/
+0
2015-08-08
ddr: altera: sequencer: Pluck out RW_MGR_* macros from code
Marek Vasut
1
-8
/
+8
2015-08-08
ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS
Marek Vasut
1
-1
/
+0
2015-08-08
ddr: altera: sequencer: Zap unused params and macros
Marek Vasut
1
-27
/
+4
2015-08-08
ddr: altera: Clean up mem_config()
Marek Vasut
1
-4
/
+0
2015-08-08
ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
Marek Vasut
1
-4
/
+0
2015-08-08
ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
Marek Vasut
1
-5
/
+5
2015-08-08
ddr: altera: Pluck out remaining sdr_get_addr() calls
Marek Vasut
1
-34
/
+19
2015-08-08
driver/ddr/altera: Add the sdram calibration portion
Dinh Nguyen
1
-0
/
+322