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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
drivers
/
timer
/
tsc_timer.c
Age
Commit message (
Expand
)
Author
Files
Lines
2018-08-20
x86: tsc: Try hardware calibration first
Bin Meng
1
-11
/
+16
2018-07-02
x86: timer: tsc: Allow specifying clock rate from device tree again
Bin Meng
1
-2
/
+11
2018-06-13
x86: tsc: add support for reading CPU freq from cpuid
Christian Gmeiner
1
-5
/
+24
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2017-09-16
dm: x86: Allow TSC timer to be used before DM is ready
Simon Glass
1
-5
/
+25
2017-09-16
x86: tsc: Add Airmont reference clock values
Bin Meng
1
-7
/
+10
2017-08-01
x86: tsc: Rename try_msr_calibrate_tsc() to cpu_mhz_from_msr()
Bin Meng
1
-4
/
+9
2017-08-01
x86: tsc: Correct Silvermont reference clock values
Bin Meng
1
-4
/
+4
2017-08-01
x86: tsc: Update comments and expand definitions in freq_desc_tables[]
Bin Meng
1
-15
/
+9
2017-08-01
x86: tsc: Remove the fail handling in try_msr_calibrate_tsc()
Bin Meng
1
-9
/
+0
2017-08-01
x86: tsc: Identify Intel-specific code
Bin Meng
1
-0
/
+4
2017-08-01
x86: tsc: Read all ratio bits from MSR_PLATFORM_INFO
Bin Meng
1
-1
/
+1
2015-12-09
x86: Move i8254_init() to x86_cpu_init_f()
Bin Meng
1
-10
/
+0
2015-12-01
x86: tsc: Move tsc_timer.c to drivers/timer
Bin Meng
1
-0
/
+389