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2023-02-22i2c: designware_i2c: Add ACPI configure limitationMason Huo1-0/+2
As the i2c_designware_pci.c uses ACPI APIs, add the ACPI table generation configuration for its compilation. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22net: rtl8169: Add one more device IDMason Huo1-0/+3
Add the NIC device ID and adjust the bar regions. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22clk: starfive: Add PCIe clocks for PCIe controllerMason Huo1-0/+43
Add the stg clocks for PCIe controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-22pci: Add Starfive JH7110 pcie driverMason Huo3-0/+520
Port the JH7110 pcie host driver from linux kernel. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-17vout:dc8200: add vout mipi driverkeith.zhao17-2/+3479
add vout mipi pipeline driver in uboot Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17i2c:desigware-snps: add i2c clock configkeith.zhao3-5/+28
add clock config for i2c2 and i2c5 update the i2c driver clock config Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17power: add power subsystem driver in ubootkeith.zhao9-0/+459
add power subsystem in driver,include pmu pmic and regulator pmu : dc8200 power pmic : mipi power regulator : entend power Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt3-0/+64
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-01-06Merge branch 'CR_3006_OTP_yanhong.wang' into 'jh7110-master'andy.hu1-3/+12
CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read See merge request sdk/u-boot!21
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-198/+433
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-03misc: OTP: Starfive-jh7110: update the return value of starfive_otp_readYanhong Wang1-3/+12
Update the return value to match the function prototype definition. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2022-11-21pinctrl: starfive: Add StarFive JH7110 driverKuan Lim Lee8-0/+1028
Add pinctrl driver for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-01net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dtsSamin Guo1-173/+269
support use original or inverted RGMII_TX_CLK delay train. 10M/100M/1000M can be configured independently. tx_inverted_xx = val; For example: &gmac0 { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { tx_inverted_10 = <0>; tx_inverted_100 = <1>; tx_inverted_1000 = <1>; }; }; 0: original (default) 1: inverted Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18ram: starfive: Make DDR driver support 8G sizeYan Hong Wang4-733/+547
This patch include four items: 1.rename the driver compatible name. 2.reset action with the common API. 3.clean up code to make it is closer to readable. 4.add configuration to support 8G size Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18ram: starfive: jh7110: Replace the configuration operation for pll1 clkYan Hong Wang2-27/+6
Replace the configuration operation for pll1 clk with common api provide by pll module. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk: starfive: jh7110: Modify the parameters of clk_register()Yan Hong Wang1-34/+11
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: update apb_bus clk relationshipyanhong.wang1-26/+7
The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: Make ddr driver support 2G sizeyanhong.wang4-25/+250
The ddr driver include two configs with 2G and 4G.Fist read the ddr size config from the memory node in the dts,then match the right config and do it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive:jh7110: Delete redundant logicyanhong.wang1-28/+1
In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,one group is active high, and the other group is active low. However, the software does not need to distinguish whether the RESET signal is active high or active low,Write 1 to be assert, and write 0 to deassert. Therefore, the software does not need to add additional logic to distinguish these two sets of signals. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: pll0 dynamically gets the frequencysamin1-5/+35
pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18SPL:reset:starfive-jh7110: support reset in SPLyanhong.wang2-1/+9
Update Kconfig to support reset in SPL for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:riscv:starfive: update uart3-uart5 clksyanhong.wang1-16/+24
Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18serial: ns16550: support a list of clkyanhong.wang1-0/+12
Add a list of clk enable operation. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-6/+4
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: change tx delay configyanhong.wang1-1/+1
Modify the tx delay configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: add JH7110_GMAC1_GTXC clkyanhong.wang1-0/+4
Add JH7110_GMAC1_GTXC clk for GMAC1 on JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:dwc_eth_qos:starfive: remove phy-reset-gpio setyanhong.wang1-18/+1
Phy-reset-gpio set is unused in JH7110 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: add ddr driveryanhong.wang10-0/+3203
Add driver for JH7110 to support ddr initialization in SPL. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: update clk inityanhong.wang1-96/+23
Modify the clk init code for StarFive JH7110 platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang1-3/+7
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add delay chainyanhong.wang1-12/+26
Add tx/rx delay chain for YUTAI 8521 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macrosyanhong.wang1-2/+2
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macroyanhong.wang1-1/+1
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: remove unused clkyanhong.wang1-52/+4
Remove unused clock in order to reduce code size. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy inityanhong.wang1-0/+3
Add phy init for YUTAI YT8511/YT8521. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy driveryanhong.wang3-0/+292
This adds basic support for YUTAI YT8511/YT8521 phy. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18usb:cdns3:Add StarFive wrapper driver for CDNS USB3 controlleryanhong.wang3-0/+88
Add driver to handle StarFive specific wrapper for Cadence USB3 controller present on JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive: Adjust judgment conditionsyanhong.wang1-4/+5
The serial driver will call reset driver, udelay function will be called in reset driver, but the timer is not init,so udelay function call will cases error. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy: add 10/100M register configurationyanhong.wang2-0/+14
Support 10/100M configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: add jh7110 supportyanhong.wang2-0/+290
Add new configuration for jh7110 soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18mtd:spi-nor-ids: Add support for GD25LQ256Dyanhong.wang2-0/+6
Adds support for GigaDevice's spi nor flash Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Add clock driver for JH7110yanhong.wang5-0/+708
Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18misc:OTP:Starfive-jh7110: Add driver for the Starfive otp controlleryanhong.wang3-0/+196
Added a misc driver to handle OTP memory in Starfive SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang3-0/+171
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18Reset:Starfive-jh7110: Add reset driver for JH7110yanhong.wang3-0/+253
Support for reset controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut1-0/+3
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
2021-09-28mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard5-20/+15
nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0Marek Vasut1-1/+1
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems silently defaulted to SF bus mode 0. Now the mode is always updated, which causes breakage. It seems most SF which are used as boot media operate in bus mode 0, so switch that as the default. This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked as those might need mode 3. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Cc: Andreas Biessmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Tom Rini <trini@konsulko.com> Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Cc: Vignesh Raghavendra <vigneshr@ti.com>
2021-09-28mtd: spi: nor: force mtd name to "nor%d"Patrick Delaunay1-3/+14
Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27phy: marvell: cp110: Support SATA invert polarityDenis Odintsov1-1/+6
In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <shiva@mail.ru> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
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