blob: 1b0156e503c943801783129aeee4f48a7dd6b949 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
/dts-v1/;
#include "mscc,ocelot_pcb.dtsi"
/ {
model = "Ocelot PCB123 Reference Board";
compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
chosen {
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
status_green {
label = "pcb123:green:status";
gpios = <&sgpio 43 1>; /* p11.1 */
default-state = "on";
};
status_red {
label = "pcb123:red:status";
gpios = <&sgpio 11 1>; /* p11.0 */
default-state = "off";
};
};
};
&sgpio {
status = "okay";
mscc,sgpio-ports = <0x00FFFFFF>;
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
&switch {
ethernet-ports {
port0: port@0 {
reg = <2>;
phy-handle = <&phy2>;
};
port1: port@1 {
reg = <3>;
phy-handle = <&phy3>;
};
port2: port@2 {
reg = <0>;
phy-handle = <&phy0>;
};
port3: port@3 {
reg = <1>;
phy-handle = <&phy1>;
};
};
};
|
