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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 StarFive Technology Co., Ltd. */
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "starfive,dubhe";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "starfive,dubhe", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x0>;
riscv,isa = "rv64imafdcbh_sscofpmf";
tlb-split;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "starfive,dubhe", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x1>;
riscv,isa = "rv64imafdcbh_sscofpmf";
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
l2_cache0: cache-controller-0 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-unified;
};
l2_cache1: cache-controller-1 {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-unified;
};
};
pmu {
compatible = "riscv,pmu";
interrupts-extended = <&cpu0_intc 13>, <&cpu1_intc 13>;
riscv,event-to-mhpmevent = <0x00005 0x0000 0xA>,
<0x00006 0x0000 0xB>,
<0x00008 0x0000 0x10>,
<0x00009 0x0000 0xF>,
<0x10000 0x0000 0x19>,
<0x10001 0x0000 0x1A>,
<0x10002 0x0000 0x1B>,
<0x10003 0x0000 0x1C>,
<0x10008 0x0000 0x8>,
<0x10009 0x0000 0x9>,
<0x1000C 0x0000 0x9E>,
<0x1000D 0x0000 0x9F>,
<0x10010 0x0000 0x1D>,
<0x10011 0x0000 0x1E>,
<0x10012 0x0000 0x1F>,
<0x10013 0x0000 0x20>,
<0x10014 0x0000 0x21>,
<0x10018 0x0000 0x17>,
<0x10019 0x0000 0x18>,
<0x10020 0x0000 0x8>,
<0x10021 0x0000 0x7>;
riscv,event-to-mhpmcounters = <0x00005 0x00006 0x00007FF8>,
<0x00008 0x00009 0x00007FF8>,
<0x10000 0x10003 0x00007FF8>,
<0x10008 0x10009 0x00007FF8>,
<0x1000C 0x1000D 0x00007FF8>,
<0x10010 0x10014 0x00007FF8>,
<0x10018 0x10019 0x00007FF8>,
<0x10020 0x10021 0x00007FF8>;
riscv,raw-event-to-mhpmcounters =
<0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>, /* Event ID 1-31 */
<0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>, /* Event ID 32-33 */
<0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>; /* Event ID 34 */
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
dma-noncoherent;
ranges;
clint: clint@2000000 {
#interrupt-cells = <1>;
compatible = "riscv,clint0";
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts-extended = <&cpu0_intc 3>,
<&cpu0_intc 7>,
<&cpu1_intc 3>,
<&cpu1_intc 7>;
};
pbus_clk: subsystem_pbus_clock {
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "pbus_clock";
compatible = "fixed-clock";
};
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,max-priority = <15>;
riscv,ndev = <25>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu0_intc 9>,
<&cpu1_intc 11>,
<&cpu1_intc 9>;
};
spi0: spi@10000000 {
compatible = "sifive,spi0";
reg = <0x0 0x10000000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <7>;
clocks = <&pbus_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
qspi1: spi@10010000 {
compatible = "sifive,spi0";
reg = <0x0 0x10010000 0x0 0x1000>,
<0x0 0x20000000 0x0 0x8000000>;
interrupt-parent = <&plic0>;
interrupts = <6>;
clocks = <&pbus_clk>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@10012000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic0>;
interrupts = <5>;
reg = <0x0 0x10012000 0x0 0x1000>;
clocks = <&pbus_clk>;
status = "disabled";
};
stmmac_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <256 128 64 32 0 0 0>;
};
gmac0: gmac0@10100000 {
compatible = "starfive,dubhe-eqos-5.20";
reg = <0x0 0x10100000 0x0 0x10000>;
clock-names = "gtx",
"tx",
"ptp_ref",
"stmmaceth",
"pclk",
"gtxc";
interrupt-parent = <&plic0>;
interrupts = <8>, <11>, <12> ;
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
max-frame-size = <1500>;
phy-mode = "rgmii-id";
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
rx-fifo-depth = <2048>;
tx-fifo-depth = <2048>;
snps,fixed-burst;
snps,no-pbl-x8;
snps,force_thresh_dma_mode;
snps,axi-config = <&stmmac_axi_setup>;
snps,tso;
snps,en-tx-lpi-clockgating;
snps,txpbl = <4>;
snps,rxpbl = <4>;
status = "disabled";
};
};
};
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