summaryrefslogtreecommitdiff
path: root/arch/riscv/lib/andes_plic.c
blob: 20529ab3eb58899ffca8790558494e34e9a370b3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
 *
 * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
 * The PLIC block holds memory-mapped claim and pending registers
 * associated with software interrupt.
 */

#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/syscon.h>
#include <cpu.h>
#include <linux/err.h>

/* pending register */
#define PENDING_REG(base, hart)	((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
/* enable register */
#define ENABLE_REG(base, hart)	((ulong)(base) + 0x2000 + (hart) * 0x80)
/* claim register */
#define CLAIM_REG(base, hart)	((ulong)(base) + 0x200004 + (hart) * 0x1000)

#define ENABLE_HART_IPI         (0x80808080)
#define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))

DECLARE_GLOBAL_DATA_PTR;
static int init_plic(void);

#define PLIC_BASE_GET(void)						\
	do {								\
		long *ret;						\
									\
		if (!gd->arch.plic) {					\
			ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
			if (IS_ERR(ret))				\
				return PTR_ERR(ret);			\
			gd->arch.plic = ret;				\
			init_plic();					\
		}							\
	} while (0)

static int enable_ipi(int hart)
{
	unsigned int en;

	en = ENABLE_HART_IPI >> hart;
	writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));

	return 0;
}

static int init_plic(void)
{
	struct udevice *dev;
	ofnode node;
	int ret;
	u32 reg;

	ret = uclass_find_first_device(UCLASS_CPU, &dev);
	if (ret)
		return ret;

	if (ret == 0 && dev) {
		ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
			const char *device_type;

			device_type = ofnode_read_string(node, "device_type");
			if (!device_type)
				continue;

			if (strcmp(device_type, "cpu"))
				continue;

			/* skip if hart is marked as not available */
			if (!ofnode_is_available(node))
				continue;

			/* read hart ID of CPU */
			ret = ofnode_read_u32(node, "reg", &reg);
			if (ret == 0)
				enable_ipi(reg);
		}

		return 0;
	}

	return -ENODEV;
}

int riscv_send_ipi(int hart)
{
	unsigned int ipi;

	PLIC_BASE_GET();

	ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
	writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
				gd->arch.boot_hart));

	return 0;
}

int riscv_clear_ipi(int hart)
{
	u32 source_id;

	PLIC_BASE_GET();

	source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
	writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));

	return 0;
}

int riscv_get_ipi(int hart, int *pending)
{
	PLIC_BASE_GET();

	*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
						     gd->arch.boot_hart));
	*pending = !!(*pending & SEND_IPI_TO_HART(hart));

	return 0;
}

static const struct udevice_id andes_plic_ids[] = {
	{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
	{ }
};

U_BOOT_DRIVER(andes_plic) = {
	.name		= "andes_plic",
	.id		= UCLASS_SYSCON,
	.of_match	= andes_plic_ids,
	.flags		= DM_FLAG_PRE_RELOC,
};