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| author | William Qiu <william.qiu@starfivetech.com> | 2023-12-22 12:45:47 +0300 |
|---|---|---|
| committer | Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2024-04-13 23:33:32 +0300 |
| commit | 47e36feba470ae10b06841753c3747e9fcf2d149 (patch) | |
| tree | f25580278028560c847ef833db12ba294aee5007 | |
| parent | 2a607367e76cf4e2f212424851439f5c78eaba98 (diff) | |
| download | linux-47e36feba470ae10b06841753c3747e9fcf2d149.tar.xz | |
riscv: dts: starfive: jh7100: Add PWM node and pins configuration
Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 1 board.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit 5e598b99fedf57858a98c5edf9da55e378910781)
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 24 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 |
2 files changed, 33 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index 42fb61c36068..6aac0404b465 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -115,6 +115,24 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(7, + GPO_PWM_PAD_OUT_BIT0, + GPO_PWM_PAD_OE_N_BIT0, + GPI_NONE)>, + <GPIOMUX(5, + GPO_PWM_PAD_OUT_BIT1, + GPO_PWM_PAD_OE_N_BIT1, + GPI_NONE)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + sdio0_pins: sdio0-0 { clk-pins { pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT, @@ -257,6 +275,12 @@ clock-frequency = <27000000>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sdio0 { broken-cd; bus-width = <4>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 5d499d8aa804..667ab0d58850 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -324,6 +324,15 @@ <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>; |