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| author | George Hung <george.hung@quantatw.com> | 2019-05-23 15:27:33 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2021-11-01 09:42:43 +0300 |
| commit | 00d5d14c757832693f3cc61f846ecb61a3c95590 (patch) | |
| tree | 0095311e2b3ffd3cf4ee1c93ff40dbdc443a6179 /MAINTAINERS | |
| parent | c58e7600fd616dc55f6e4d64a715eae2903f1f8f (diff) | |
| download | linux-00d5d14c757832693f3cc61f846ecb61a3c95590.tar.xz | |
edac: npcm: Add Nuvoton NPCM7xx EDAC driver
Add support for the Nuvoton NPCM7xx SoC EDAC driver
NPCM7xx ECC datasheet from nuvoton.israel-Poleg:
"Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories"
Tested: Forcing an ECC error event
Write a value to the xor_check_bits parameter that will trigger
an ECC event once that word is read
For example, to force a single-bit correctable error on bit 0 of
the user-word space shown, write 0x75 into that byte of the
xor_check_bits parameter and then assert fwc (force write check)
bit to 'b1' (mem base: 0xf0824000, xor_check_bits reg addr: 0x178)
$ devmem 0xf0824178 32 0x7501
To force a double-bit un-correctable error for the user-word space,
write 0x03 into that byte of the xor_check_bits parameter
$ devmem 0xf0824178 32 0x301
OpenBMC-Staging-Count: 9
Signed-off-by: George Hung <george.hung@quantatw.com>
Reviewed-by: Avi Fishman <avifishman70@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 65ae77cd5ac8..5aef58894e9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6796,6 +6796,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/mpc85xx_edac.[ch] +EDAC-NPCM7XX +M: George Hung <george.hung@quantatw.com> +S: Maintained +F: drivers/edac/npcm7xx_edac.c +F: Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt + EDAC-PASEMI M: Egor Martovetsky <egor@pasemi.com> L: linux-edac@vger.kernel.org |