Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2020-05-29 | clk: Ingenic: Adjust cgu code to make it compatible with X1830. | 周琰杰 (Zhou Yanjie) | 1 | -0/+4 |
2019-08-12 | clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro | Paul Cercueil | 1 | -1/+1 |
2019-06-26 | clk: ingenic: Handle setting the Low-Power Mode bit | Paul Cercueil | 1 | -0/+3 |
2019-06-07 | clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly | Paul Cercueil | 1 | -1/+8 |
2019-06-07 | clk: ingenic/jz4725b: Fix incorrect dividers for main clocks | Paul Cercueil | 1 | -5/+24 |
2019-04-11 | clk: ingenic: jz4725b: Add UDC PHY clock | Paul Cercueil | 1 | -0/+6 |
2018-10-17 | clk: Add Ingenic jz4725b CGU driver | Paul Cercueil | 1 | -0/+225 |