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Before this change JTAG HW2 mode shift operation failed to process a
shift request when current state was Exit IR/DR for the same type of
xfer SHIFTIR/SHIFTDR respectively. After this change we will
support shift operations in HW2 mode from the following jtag states:
For SHIFTDR: JTAG_STATE_SHIFTDR, JTAG_STATE_IDLE, JTAG_STATE_TLRESET,
JTAG_STATE_PAUSEDR, JTAG_STATE_EXIT1DR and
JTAG_STATE_EXIT1IR
For SHIFTIR: JTAG_STATE_SHIFTIR, JTAG_STATE_IDLE, JTAG_STATE_TLRESET,
JTAG_STATE_PAUSEIR, JTAG_STATE_EXIT1IR and
JTAG_STATE_EXIT1DR
Test:
ASD Sanity(SW mode) finished successfully(SPR)
ASD Sanity(HW mode) finished successfully(SPR)
Cscripts(SW mode) finished successfully(SPR)
Cscripts(HW mode) finished successfully(SPR)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Ide878b8986639c63e41c2bc360e06a261cdffee5
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Previous this change we send JTAG state machine to RTI in all shifts
that end state was EXIT1IR/EXIT1DR. With this rule we were able to
guarantee a smooth chain transition in HW mode (chain is expected to
be in RTI after chain has been selected). However, there were
uncovered cases such as Go to Ex1IR and then Go to ShfDR which
doesn't expect to visit RTI.
With this change AST26xx shift behavior in HW mode will be more
accurate to what it is being requested. JTAG state machine will
remain in EXIT1IR/EXIT1DR when those end states are being sent to
the aspeed_jtag_xfer_hw2 driver function.
It is now expected that ASD application calculates the right end
state and send either EXIT1IR, EXIT1DR, RTI or PAUSEDR to control
shift operations and JTAG state transitions in HW mode.
Additionally aspeed_jtag_set_tap_state_hw2() function was updated to
handle go to RTI from EXIT1 included in two different network
packets.
Tested:
Using Software, HW1 and HW2 modes:
ASD Sanity ended successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Ic49b0ce26c49d08e806c29e5ae72a4b3b7e68553
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To avoid conflicts with other JTAG hardware probes such as XDP, ASD
must disable JTAG Master controller output when ASD connection is not
in use.
This commit fixes the output disable for AST26xx series which needs
ASPEED_JTAG_CTRL and ASPEED_JTAG_GBLCTRL to be cleared for all SW,
HW1 and HW2 modes.
Test:
1. Run jtag_test
2. Run ASD Sanity(using XDP) - Failed here before
3. Run jtag_test
4. Run ASD Sanity(using ASD)
5. Run ASD Sanity(using XDP) - Failed here before
6. ASD Sanity(using ASD)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: I4f403f4b8412ab96cee195412cc412360845b6d0
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Using an overshift test environment where we execute a continuous
JTAG R/W operation during hours we discover that in one of million
ocurences for AST26xx TDO read occurred before JTAG Master controller
reflected real tdo value on ASPEED_JTAG_SW.
It was needed to add two delays during the SW xfer process to
prevent this issue. We tested several delay options and found that
using a read/write to ASPEED_JTAG_PADCTRL1(not used in SW mode)
register gives the JTAG Master controller enough time to process
the xfer with the lowest performance impact among the delay options.
For AST25xx an extra delay was not required.
Test:
All of the following in SW mode:
AST26xx(SPR) ASD Sanity finished successfully.
AST26xx(SPR) Overshift test with 4K iterations finished successfully.
AST26xx(SPR) jtag_test with 8M iterations finished successfully.
AST25xx(ICX) ASD Sanity finished successfully
AST25xx(ICX) jtag_test with 8M iterations finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Change-Id: Idf82632a564495e0a69075c9b842e84d39419612
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- Move TDI state matrix to core header file
- These changes are done based on feedback from Paul
Fertser, from the OpenOCD.
Test:
SPR ASD Sanity and jtag_test finished successfully.
ICX ASD Sanity and jtag_test finished successfully.
Change-Id: Idb612e50d5a8ea5929f7c9241d279c345587983a
Signed-off-by: Castro, Omar Eduardo <omar.eduardo.castro@intel.com>
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JTAG xfer length is measured in bits and it is allowed to send non 8-bit
aligned xfers. For such xfers we will read the content of the remaining
bits in the last byte of tdi buffer and restore those bits along with
the xfer readback.
Add also linux types to JTAG header to remove external dependencies.
Test:
SPR ASD Sanity and jtag_test finished successfully.
SKX ASD Sanity and jtag_test finished successfully.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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Create a low level function to handle xfer interrupts and map
corresponding interrupt functions for AST25xx and AST26xx in
HW1 and HW2 xfer modes.
By default JTAG driver still uses polling. Interrupt support
needs to be enabled with USE_INTERRUPTS macro.
Remove also unused SCU reference.
Test:
AST26xx(SPR) ASD Sanity and jtag_test using HW2 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 polling.
AST26xx(SPR) ASD Sanity and jtag_test using HW2 interrupt.
AST26xx(SPR) ASD Sanity and jtag_test using HW1 interrupt.
AST26xx(SPR) jtag_test using SW mode.
AST25xx(SKX) ASD Sanity and jtag_test using HW polling.
AST25xx(SKX) ASD Sanity and jtag_test using HW interrupt.
AST25xx(SKX) jtag_test using SW mode.
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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There is a data to send/read FIFO used by the AST26xx series JTAG Master
Controller when hardware mode 1 and 2 transfer is selected. The proper
usage of this FIFO allows AST26xx JTAG peripheral to xfer up to 512 bit
without CPU interaction.
In this commit we included a delay after FIFO R/W operations to provide
enough time for JTAG master controller to handle FIFO transitions.
Additionally we included aspeed_jtag_xfer_hw_26xx() to separate AST25xx
and AST26xx HW1 xfer handlers and setup the delay only for AST26xx
series.
These changes doesn't affect Software mode or AST25xx functionality.
Tested:
ASD Sanity works finished successfully for AST26xx in SW/HW1/HW2 modes
50 times jtag_test -h -t 8 -i 8000000 (HW2)
50 times jtag_test -h -t 8 -i 8000000 (HW1)
50 times jtag_test -i 8000000 (SW)
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
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Driver adds support of Aspeed 2400-2600 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- status_set
- xfer;
- mode_set;
- bitbang;
- enable;
- disable;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
It has also been tested on Intel system using Aspeed 25xx SoC
for JTAG communication.
Tested on Intel system using Aspeed 26xx SoC for JTAG communication.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Steven Filary <steven.a.filary@intel.com>
Cc: Vadim Pasternak <vadimp@mellanox.com>
Cc: Amithash Prasad <amithash@fb.com>
Cc: Patrick Williams <patrickw3@fb.com>
Cc: Rgrs <rgrs@protonmail.com>
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JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- GIOCSTATUS read the current TAPC state of the JTAG controller
- SIOCSTATE Forces the JTAG TAPC to go into a particular state.
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
- IOCBITBANG for low level control of JTAG signals.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: William Breathitt Gray <vilhelm.gray@gmail.com>
Cc: Federico Vaga <federico.vaga@cern.ch>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Christian Gromm <christian.gromm@microchip.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Yiwei Zhang <zzyiwei@google.com>
Cc: Alessandro Rubini <rubini@gnudd.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Steven Filary <steven.a.filary@intel.com>
Cc: Vadim Pasternak <vadimp@mellanox.com>
Cc: Amithash Prasad <amithash@fb.com>
Cc: Patrick Williams <patrickw3@fb.com>
Cc: Rgrs <rgrs@protonmail.com>
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