diff options
Diffstat (limited to 'meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files')
13 files changed, 408 insertions, 560 deletions
diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch deleted file mode 100644 index 2ec774144..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0000-AST2600-Add-the-latest-chip-initialization-code.patch +++ /dev/null @@ -1,265 +0,0 @@ -From 8c9e2fffa9ea72ddc8734ee74b30cc62ba06fd3a Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> -Date: Mon, 2 Mar 2020 13:54:50 -0800 -Subject: [PATCH] AST2600: Add the latest chip initialization code - -This commit cherry picked the latest chip initialization code from -Aspped SDK v00.05.05 to support AST2600 A1 revision. - -Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> ---- - arch/arm/mach-aspeed/ast2600/Makefile | 2 +- - arch/arm/mach-aspeed/ast2600/cache.c | 26 +++++++ - arch/arm/mach-aspeed/ast2600/platform.S | 132 +++++++++++++++++++++++++------- - 3 files changed, 130 insertions(+), 30 deletions(-) - create mode 100644 arch/arm/mach-aspeed/ast2600/cache.c - -diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile -index b074d4b70a14..2889388fab75 100644 ---- a/arch/arm/mach-aspeed/ast2600/Makefile -+++ b/arch/arm/mach-aspeed/ast2600/Makefile -@@ -1,2 +1,2 @@ --obj-y += platform.o aspeed_scu_info.o -+obj-y += platform.o aspeed_scu_info.o cache.o - obj-$(CONFIG_SPL_BUILD) += spl.o -diff --git a/arch/arm/mach-aspeed/ast2600/cache.c b/arch/arm/mach-aspeed/ast2600/cache.c -new file mode 100644 -index 000000000000..82de0b0fda8a ---- /dev/null -+++ b/arch/arm/mach-aspeed/ast2600/cache.c -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) ASPEED Technology Inc. -+ * Chia-Wei Wang <chiawei_wang@aspeedtech.com> -+ */ -+ -+#include <common.h> -+#include <asm/system.h> -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+void enable_caches(void) -+{ -+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -+ enum dcache_option opt = DCACHE_WRITETHROUGH; -+#else -+ enum dcache_option opt = DCACHE_WRITEBACK; -+#endif -+ /* enable D-cache as well as MMU */ -+ dcache_enable(); -+ -+ /* setup cache attribute for DRAM region */ -+ mmu_set_region_dcache_behaviour(ASPEED_DRAM_BASE, -+ gd->ram_size, -+ opt); -+} -diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index de97cccc78b7..f1a1f057c09b 100644 ---- a/arch/arm/mach-aspeed/ast2600/platform.S -+++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -26,39 +26,45 @@ - * +----------------------+ AST_SMP_MAILBOX_BASE - */ - --#define AST_SMP_MAILBOX_BASE 0x1E6E2180 -+#define AST_SMP_MAILBOX_BASE (0x1E6E2180) - #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) - #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) - #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) - #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) - - /* AST2600 HW registers */ --#define AST_SCU_BASE 0x1E6E2000 --#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) --#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) --#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) --#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) --#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) --#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) --#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) --#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) -- --#define AST_FMC_BASE 0x1E620000 -+#define AST_SCU_BASE (0x1E6E2000) -+#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) -+#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) -+#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) -+#define AST_SCU_SYSRST_CTRL (AST_SCU_BASE + 0x040) -+#define AST_SCU_SYSRST_CTRL_CLR (AST_SCU_BASE + 0x044) -+#define AST_SCU_DEBUG_CTRL (AST_SCU_BASE + 0x0C8) -+#define AST_SCU_DEBUG_CTRL2 (AST_SCU_BASE + 0x0D8) -+#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) -+#define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) -+#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) -+#define AST_SCU_HW_STRAP1_CLR (AST_SCU_BASE + 0x504) -+#define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510) -+#define AST_SCU_HW_STRAP2_CLR (AST_SCU_BASE + 0x514) -+#define AST_SCU_CA7_CTRL (AST_SCU_BASE + 0x800) -+#define AST_SCU_CA7_AXI_PREFETCH_START (AST_SCU_BASE + 0x808) -+#define AST_SCU_CA7_AXI_PREFETCH_END (AST_SCU_BASE + 0x80C) -+#define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) -+#define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) -+#define AST_SCU_MMIO_DEC_SET (AST_SCU_BASE + 0xC24) -+ -+#define AST_FMC_BASE (0x1E620000) -+#define AST_FMC_CE0_CTRL (AST_FMC_BASE + 0x010) - #define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) - #define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) - -+#define AST_GPIO_BASE (0x1E780000) -+#define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) -+ - /* Revision ID */ - #define REV_ID_AST2600A0 0x05000303 - --ENTRY(ast_bootmode) -- ldr r1, =AST_SCU_HW_STRAP1 -- ldr r0, [r1] -- tst r0, #0x4 -- moveq r0, #0x0 @; AST_BOOTMODE_SPI -- movne r0, #0x1 @; AST_BOOTMODE_EMMC -- mov pc, lr --ENDPROC(ast_bootmode) -- - .macro scu_unlock - movw r0, #0xA8A8 - movt r0, #0x1688 @; magic key to unlock SCU -@@ -71,11 +77,19 @@ ENDPROC(ast_bootmode) - - .macro timer_init - #ifdef CONFIG_FPGA_ASPEED -- movw r0, #0x7840 -- movt r0, #0x17D -+ movw r0, #0xF080 -+ movt r0, #0x2FA - #else -- movw r0, #0x2340 -- movt r0, #0x430E -+ ldr r0, =AST_SCU_REV_ID -+ ldr r0, [r0] -+ -+ ldr r1, =REV_ID_AST2600A0 -+ cmp r0, r1 -+ -+ movweq r0, #0x32C0 -+ movteq r0, #0x4013 -+ movwne r0, #0x8C00 -+ movtne r0, #0x4786 - #endif - mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ - .endm -@@ -133,7 +147,7 @@ do_primary_core_setup: - /* unlock system control unit */ - scu_unlock - -- /* tune-up CPU clock for AST2600 A0 */ -+ /* identify AST2600 A0/A1 */ - ldr r0, =AST_SCU_REV_ID - ldr r0, [r0] - -@@ -142,7 +156,7 @@ do_primary_core_setup: - - bne 0f - -- /* setup CPU clocks */ -+ /* tune up CPU clocks (A0 only) */ - ldr r0, =AST_SCU_HW_STRAP1 - ldr r1, [r0] - bic r1, #0x1800 -@@ -150,7 +164,7 @@ do_primary_core_setup: - str r1, [r0] - - ldr r0, =AST_SCU_HPLL_PARAM -- movw r1, #0x4087 -+ movw r1, #0x4080 - movt r1, #0x1000 - str r1, [r0] - -@@ -163,13 +177,54 @@ wait_lock: - tst r1, #0x80000000 - beq wait_lock - -+ /* skip A1 only area */ -+ b 1f -+ - 0: -+ /* enable AXI prefetch (A1 only) */ -+ ldr r0, =AST_SCU_CA7_AXI_PREFETCH_START -+ ldr r1, =ASPEED_DRAM_BASE -+ str r1, [r0] -+ -+ ldr r0, =AST_SCU_CA7_AXI_PREFETCH_END -+ ldr r1, =0xFFFFFFFF -+ str r1, [r0] -+ -+ ldr r0, =AST_SCU_CA7_CTRL -+ ldr r1, [r0] -+ orr r1, #0x8000 -+ str r1, [r0] -+ -+ /* LPC/eSPI mode selection (A1 only) */ -+ ldr r0, =AST_GPIOYZ_DATA_VALUE -+ ldr r0, [r0] -+ tst r0, #0x1000 -+ beq 1f -+ -+ /* switch to LPC mode if GPIOZ[4]=1 */ -+ ldr r0, =AST_SCU_HW_STRAP2 -+ ldr r1, [r0] -+ orr r1, #0x40 -+ str r1, [r0] -+ -+1: -+ /* release display port reset */ -+ ldr r0, =AST_SCU_SYSRST_CTRL_CLR -+ movw r1, #0x0000 -+ movt r1, #0x3000 -+ str r1, [r0] -+ -+ /* MMIO decode setting */ -+ ldr r0, =AST_SCU_MMIO_DEC_SET -+ mov r1, #0x2000 -+ str r1, [r0] -+ - /* enable cache & SRAM parity check */ - mov r0, #0 - ldr r1, =AST_SCU_CA7_PARITY_CLR - str r0, [r1] - -- mov r0, #0x11 -+ mov r0, #0x1 - ldr r1, =AST_SCU_CA7_PARITY_CHK - str r0, [r1] - -@@ -177,8 +232,27 @@ wait_lock: - mov r0, #0 - ldr r1, =AST_FMC_WDT1_CTRL_MODE - str r0, [r1] -+#if 0 - ldr r1, =AST_FMC_WDT2_CTRL_MODE - str r0, [r1] -+#endif -+ /* tune up SPI clock */ -+ movw r0, #0x0641 -+ movt r0, #0x203B -+ ldr r1, =AST_FMC_CE0_CTRL -+ str r0, [r1] -+ -+ /* disable UART-based SoC Debug Interface UART5 and P2A bridge*/ -+ ldr r0, =AST_SCU_DEBUG_CTRL -+ ldr r1, [r0] -+ orr r1, #0x03 -+ str r1, [r0] -+ -+ /* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */ -+ ldr r0, =AST_SCU_DEBUG_CTRL2 -+ ldr r1, [r0] -+ orr r1, #0x0A -+ str r1, [r0] - - /* relocate mailbox insn. for cpuN polling SMP go signal */ - adrl r0, mailbox_insn --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch index f1505b8cd..373893a44 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch @@ -1,4 +1,4 @@ -From efa949f82a1dd32b83eafe3fe58038abc04ecdbf Mon Sep 17 00:00:00 2001 +From 145ffdf95955562eddf96d0342bcdebd98f8dc95 Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@intel.com> Date: Thu, 24 Oct 2019 14:06:33 -0700 Subject: [PATCH] Add ast2600-intel as a new board @@ -7,23 +7,20 @@ Signed-off-by: Vernon Mauery <vernon.mauery@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> --- - arch/arm/dts/Makefile | 3 + - arch/arm/dts/ast2600-intel.dts | 157 ++++++++++ - arch/arm/lib/interrupts.c | 5 + - arch/arm/mach-aspeed/ast2600/Kconfig | 9 + - arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c | 1 + - board/aspeed/ast2600_intel/Kconfig | 13 + - board/aspeed/ast2600_intel/Makefile | 4 + - board/aspeed/ast2600_intel/ast-espi.c | 298 ++++++++++++++++++ - board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++ - board/aspeed/ast2600_intel/ast-irq.h | 8 + - board/aspeed/ast2600_intel/ast-timer.c | 59 ++++ - board/aspeed/ast2600_intel/intel.c | 176 +++++++++++ - cmd/Kconfig | 2 +- - common/autoboot.c | 10 + - common/board_r.c | 8 +- - include/configs/evb_ast2600.h | 2 +- - 16 files changed, 1148 insertions(+), 6 deletions(-) + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/ast2600-intel.dts | 197 ++++++++++++++++ + arch/arm/lib/interrupts.c | 5 + + arch/arm/mach-aspeed/ast2600/Kconfig | 8 + + board/aspeed/ast2600_intel/Kconfig | 13 ++ + board/aspeed/ast2600_intel/Makefile | 4 + + board/aspeed/ast2600_intel/ast-espi.c | 298 ++++++++++++++++++++++++ + board/aspeed/ast2600_intel/ast-irq.c | 399 +++++++++++++++++++++++++++++++++ + board/aspeed/ast2600_intel/ast-irq.h | 8 + + board/aspeed/ast2600_intel/ast-timer.c | 59 +++++ + board/aspeed/ast2600_intel/intel.c | 177 +++++++++++++++ + cmd/Kconfig | 2 +- + common/autoboot.c | 10 + + 13 files changed, 1181 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/ast2600-intel.dts create mode 100644 board/aspeed/ast2600_intel/Kconfig create mode 100644 board/aspeed/ast2600_intel/Makefile @@ -34,25 +31,27 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> create mode 100644 board/aspeed/ast2600_intel/intel.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index d1d4dca340f8..38fe8113469e 100644 +index e4dae2937968..da8903123999 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -680,6 +680,9 @@ dtb-$(CONFIG_TARGET_EVB_AST2500) += \ - dtb-$(CONFIG_TARGET_EVB_AST2600) += \ - ast2600-evb.dtb - -+dtb-$(CONFIG_TARGET_AST2600_INTEL) += \ +@@ -683,7 +683,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ + ast2600-fpga.dtb \ + ast2600-rainier.dtb \ + ast2600-slt.dtb \ +- ast2600-tacoma.dtb ++ ast2600-tacoma.dtb \ + ast2600-intel.dtb -+ - dtb-$(CONFIG_TARGET_FPGA_AST2600) += \ - ast2600-fpga.dtb + + dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts new file mode 100644 -index 000000000000..99788b21e444 +index 000000000000..9a15e204f83b --- /dev/null +++ b/arch/arm/dts/ast2600-intel.dts -@@ -0,0 +1,157 @@ +@@ -0,0 +1,197 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++// Copyright (c) 2019-2020 Intel Corporation +/dts-v1/; + +#include "ast2600-u-boot.dtsi" @@ -144,14 +143,31 @@ index 000000000000..99788b21e444 + +&mdio { + status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ethphy1: ethernet-phy@1 { ++ reg = <0>; ++ }; ++ ++ ethphy2: ethernet-phy@2 { ++ reg = <0>; ++ }; ++ ++ ethphy3: ethernet-phy@3 { ++ reg = <0>; ++ }; ++ ++ ethphy4: ethernet-phy@4 { ++ reg = <0>; ++ }; +}; + +&mac1 { + status = "okay"; -+ + phy-mode = "rgmii"; ++ phy-handle = <ðphy2>; + pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>; ++ pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mac2link_default &pinctrl_mdio2_default>; +}; + +&fmc { @@ -210,6 +226,28 @@ index 000000000000..99788b21e444 + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; +}; ++ ++&i2c9 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c10_default>; ++}; ++ ++&i2c12 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c13_default>; ++}; ++ ++&i2c13 { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c14_default>; ++}; +\ No newline at end of file diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index ee775ce5d264..8c985532afb4 100644 --- a/arch/arm/lib/interrupts.c @@ -245,14 +283,13 @@ index ee775ce5d264..8c985532afb4 100644 { efi_restore_gd(); diff --git a/arch/arm/mach-aspeed/ast2600/Kconfig b/arch/arm/mach-aspeed/ast2600/Kconfig -index 3c208ff3da67..a2a2fe0e24a8 100644 +index dd991e87c795..7ccbb0b5e0ea 100644 --- a/arch/arm/mach-aspeed/ast2600/Kconfig +++ b/arch/arm/mach-aspeed/ast2600/Kconfig -@@ -24,9 +24,18 @@ config TARGET_FPGA_AST2600 - FPGA-AST2600 is Aspeed FPGA board for AST2600 chip. - This is mainly for internal development. Note that - most implementation is co-code with EVB-AST2600. -+ +@@ -51,6 +51,13 @@ config TARGET_SLT_AST2600 + help + SLT-AST2600 is Aspeed SLT board for AST2600 chip. + +config TARGET_AST2600_INTEL + bool "AST2600-INTEL" + depends on ASPEED_AST2600 @@ -262,23 +299,14 @@ index 3c208ff3da67..a2a2fe0e24a8 100644 + endchoice - source "board/aspeed/evb_ast2600/Kconfig" + source "board/aspeed/evb_ast2600a0/Kconfig" +@@ -59,5 +66,6 @@ source "board/aspeed/ncsi_ast2600a0/Kconfig" + source "board/aspeed/ncsi_ast2600a1/Kconfig" source "board/aspeed/fpga_ast2600/Kconfig" + source "board/aspeed/slt_ast2600/Kconfig" +source "board/aspeed/ast2600_intel/Kconfig" endif -diff --git a/arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c b/arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c -index c31e8a3614b0..84ca9f68aee7 100644 ---- a/arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c -+++ b/arch/arm/mach-aspeed/ast2600/aspeed_scu_info.c -@@ -88,6 +88,7 @@ extern void - aspeed_sys_reset_info(void) - { - u32 rest = readl(ASPEED_SYS_RESET_CTRL); -+ printf("RST: %08x\n", rest); - - if (rest & SYS_PWR_RESET_FLAG) { - printf("RST : Power On \n"); diff --git a/board/aspeed/ast2600_intel/Kconfig b/board/aspeed/ast2600_intel/Kconfig new file mode 100644 index 000000000000..b841dab60c76 @@ -1098,10 +1126,10 @@ index 000000000000..cf8c69aba5d3 +} diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c new file mode 100644 -index 000000000000..b5d8dd36d20b +index 000000000000..a02e246d0d81 --- /dev/null +++ b/board/aspeed/ast2600_intel/intel.c -@@ -0,0 +1,176 @@ +@@ -0,0 +1,177 @@ +/* Intel customizations of Das U-Boot */ +#include <common.h> +#include <asm/gpio.h> @@ -1139,6 +1167,7 @@ index 000000000000..b5d8dd36d20b + return value <= 0 ? 0 : 1; +} + ++#define SCU_BASE 0x1E6E2000 +int misc_init_r(void) +{ + /* This is called near the end of the _r init sequence */ @@ -1279,10 +1308,10 @@ index 000000000000..b5d8dd36d20b +} +#endif diff --git a/cmd/Kconfig b/cmd/Kconfig -index 92736f2d6612..f64a2595da65 100644 +index d5aa204290bd..89f6668b788e 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -1862,7 +1862,7 @@ config CMD_DIAG +@@ -1876,7 +1876,7 @@ config CMD_DIAG config CMD_IRQ bool "irq - Show information about interrupts" @@ -1316,45 +1345,6 @@ index 94133eaeda78..5e69000b848b 100644 if (bootdelay >= 0) abort = __abortboot(bootdelay); -diff --git a/common/board_r.c b/common/board_r.c -index 472987d5d52f..a7f5371bac71 100644 ---- a/common/board_r.c -+++ b/common/board_r.c -@@ -673,6 +673,10 @@ static init_fnc_t init_sequence_r[] = { - #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \ - defined(CONFIG_SANDBOX) - board_init, /* Setup chipselects */ -+ interrupt_init, -+#ifdef CONFIG_ARM -+ initr_enable_interrupts, -+#endif - #endif - /* - * TODO: printing of the clock inforamtion of the board is now -@@ -771,10 +775,6 @@ static init_fnc_t init_sequence_r[] = { - #ifdef CONFIG_CMD_KGDB - initr_kgdb, - #endif -- interrupt_init, --#ifdef CONFIG_ARM -- initr_enable_interrupts, --#endif - #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) - timer_init, /* initialize timer */ - #endif -diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h -index 3a12f2f0d43c..91a42f2522e2 100644 ---- a/include/configs/evb_ast2600.h -+++ b/include/configs/evb_ast2600.h -@@ -18,7 +18,7 @@ - - /* Environment */ - #define CONFIG_ENV_SIZE 0x10000 --#define CONFIG_ENV_OFFSET 0x60000 -+#define CONFIG_ENV_OFFSET 0x2400000 - #define CONFIG_ENV_SECT_SIZE (4 << 10) - - #endif /* __CONFIG_H */ -- 2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch index 88d7cd019..326f36df1 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch @@ -1,4 +1,4 @@ -From 2a52808ddd6a6bef40bab9a15bd22b1c7988a798 Mon Sep 17 00:00:00 2001 +From 3195e1ec2d772d5e4c16ae5b60c294086cfc17be Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Thu, 12 Dec 2019 12:54:18 +0800 Subject: [PATCH] ast2600: intel-layout-environment-addr @@ -9,13 +9,12 @@ Both kernel and u-boot work at the area /dev/mtd/u-boot-env Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - common/board_r.c | 11 +++++++++-- - include/configs/aspeed-common.h | 12 +++++++++++- - include/configs/evb_ast2600_spl.h | 2 +- - 3 files changed, 21 insertions(+), 4 deletions(-) + common/board_r.c | 13 ++++++++++--- + include/configs/aspeed-common.h | 11 ++++++++++- + 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/common/board_r.c b/common/board_r.c -index a7f5371bac71..492d7f1cbe4c 100644 +index 472987d5d52f..b665d0e30262 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -433,10 +433,17 @@ static int should_load_env(void) @@ -23,6 +22,8 @@ index a7f5371bac71..492d7f1cbe4c 100644 { /* initialize environment */ - if (should_load_env()) +- env_relocate(); +- else + if (should_load_env()) { + /* + * try again, in case the environment failed to load the first @@ -30,8 +31,7 @@ index a7f5371bac71..492d7f1cbe4c 100644 + */ + if (!gd->env_valid) + env_init(); - env_relocate(); -- else ++ env_relocate(); + } else { set_default_env(NULL, 0); + } @@ -39,47 +39,29 @@ index a7f5371bac71..492d7f1cbe4c 100644 env_set_hex("fdtcontroladdr", (unsigned long)map_to_sysmem(gd->fdt_blob)); diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h -index d1eb4688e68f..0ece4a1b9440 100644 +index cdbffc97a223..6065ec58db0a 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h -@@ -55,13 +55,23 @@ - #ifndef CONFIG_BOOTCOMMAND - #define CONFIG_BOOTCOMMAND "bootm 20080000" +@@ -65,9 +65,18 @@ + #endif + + #ifndef CONFIG_ENV_OFFSET +-#define CONFIG_ENV_OFFSET 0xF0000 ++#define CONFIG_ENV_OFFSET 0x2400000 #endif + +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -+#define CONFIG_ENV_ADDR_REDUND - #define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OVERWRITE ++ +#define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ -+#define CONFIG_ENV_OFFSET 0x2400000 +#define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) -+#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET_REDUND) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -+#define CONFIG_ENV_SECT_SIZE (4 << 10) - - #define CONFIG_SYS_BOOTM_LEN (0x800000 * 2) - - #define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=yes\0" \ -- "spi_dma=no\0" \ -+ "spi_dma=yes\0" \ - "" ++ + #define CONFIG_ENV_SECT_SIZE (4 << 10) /* -diff --git a/include/configs/evb_ast2600_spl.h b/include/configs/evb_ast2600_spl.h -index 8bbd6e18727a..8529f46c0b19 100644 ---- a/include/configs/evb_ast2600_spl.h -+++ b/include/configs/evb_ast2600_spl.h -@@ -19,7 +19,7 @@ - - /* Environment */ - #define CONFIG_ENV_SIZE 0x10000 --#define CONFIG_ENV_OFFSET 0x90000 -+#define CONFIG_ENV_OFFSET 0x2400000 - #define CONFIG_ENV_SECT_SIZE (4 << 10) - - #ifdef CONFIG_SPL_TINY -- 2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch new file mode 100644 index 000000000..950382544 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch @@ -0,0 +1,86 @@ +From 8dfc080bafc688ccdb3253eff79b72ad72f93761 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Fri, 3 Jan 2020 15:14:09 -0800 +Subject: [PATCH] AST2600: Adjust default GPIO settings + +- Disable GPIOC3 to prevent unexpected host failures. +- Fixed GPIOC5, GPIOG6, GPIOI0~7 and GPIOL6~7 directions and + default values. +- Disabled internal pull-down of GPIOB6. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + board/aspeed/ast2600_intel/intel.c | 50 ++++++++++++++++++++++++++++++++++++++ + 1 file changed, 50 insertions(+) + +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index eb9b3959625e..b4a3dd222f3f 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -151,6 +151,54 @@ static void sgpio_init(void) + SCU_BASE | SCU_414); + } + ++static void set_gpio_default_state(void) ++{ ++#define SCU_410 0x410 /* Multi-function Pin Control #4 */ ++#define SCU_410_RGMII3TXD1 BIT(19) ++#define GPIO_004 0x004 /* GPIO A/B/C/D Direction */ ++#define GPIO_000 0x000 /* GPIO A/B/C/D Value */ ++#define GPIO_C3 BIT(19) ++ ++ /* ++ * Set GPIOC3 as an output with value high explicitly since it doesn't ++ * have an external pull up. It uses direct register access because ++ * it's called from board_early_init_f(). ++ */ ++ writel(readl(SCU_BASE | SCU_410) & ~SCU_410_RGMII3TXD1, ++ SCU_BASE | SCU_410); ++ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C3, ++ AST_GPIO_BASE | GPIO_004); ++ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C3, ++ AST_GPIO_BASE | GPIO_000); ++ ++#define SCU_610 0x610 /* Disable internal pull-down #0 */ ++#define SCU_610_GPIOB6 BIT(14) ++ writel(readl(SCU_BASE | SCU_610) | SCU_610_GPIOB6, SCU_BASE | SCU_610); ++ ++#define GPIO_C5 BIT(21) ++ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C5, ++ AST_GPIO_BASE | GPIO_004); ++ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C5, ++ AST_GPIO_BASE | GPIO_000); ++ ++#define GPIO_024 0x024 /* GPIO E/F/G/H Direction */ ++#define GPIO_020 0x020 /* GPIO E/F/G/H Value */ ++#define GPIO_G6 BIT(22) ++ writel(readl(AST_GPIO_BASE | GPIO_024) | GPIO_G6, ++ AST_GPIO_BASE | GPIO_024); ++ writel(readl(AST_GPIO_BASE | GPIO_020) | GPIO_G6, ++ AST_GPIO_BASE | GPIO_020); ++ ++#define GPIO_074 0x074 /* GPIO I/J/K/L Direction */ ++#define GPIO_070 0x070 /* GPIO I/J/K/L Value */ ++#define GPIO_I_MASK GENMASK(7, 0) ++#define GPIO_L_MASK GENMASK(29, 28) ++ writel(readl(AST_GPIO_BASE | GPIO_074) | GPIO_I_MASK | GPIO_L_MASK, ++ AST_GPIO_BASE | GPIO_074); ++ writel(readl(AST_GPIO_BASE | GPIO_070) | GPIO_I_MASK | GPIO_L_MASK, ++ AST_GPIO_BASE | GPIO_070); ++} ++ + void espi_init(void); + int arch_interrupt_init_early(void); + +@@ -167,6 +215,8 @@ int board_early_init_f(void) + * I am not sure if it actually does anything... */ + arch_interrupt_init_early(); + ++ set_gpio_default_state(); ++ + gpio_passthru_init(); + + port80h_snoop_init(); +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch deleted file mode 100644 index d9c40fea0..000000000 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0004-Disable-crashdump-trigger-gpio.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b203aee347f6b4104a7dfbc061b195c99795451e Mon Sep 17 00:00:00 2001 -From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> -Date: Fri, 3 Jan 2020 15:14:09 -0800 -Subject: [PATCH] Disable crashdump trigger gpio - -This commit disables crashdump trigger gpio (GPIOC3) to prevent -unexpected host failures. - -Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> ---- - board/aspeed/ast2600_intel/intel.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index b6a11132448f..f095f1ecd696 100644 ---- a/board/aspeed/ast2600_intel/intel.c -+++ b/board/aspeed/ast2600_intel/intel.c -@@ -151,6 +151,27 @@ static void sgpio_init(void) - SCU_BASE | SCU_414); - } - -+static void disable_crashlog_trigger(void) -+{ -+#define SCU_410 0x410 /* Multi-function Pin Control #4 */ -+#define SCU_410_RGMII3TXD1 BIT(19) -+#define GPIO_004 0x004 /* GPIO A/B/C/D Direction */ -+#define GPIO_000 0x000 /* GPIO A/B/C/D Value */ -+#define GPIO_C3 BIT(19) -+ -+ /* -+ * Set FM_BMC_CRASHLOG_TRIG_N (GPIOC3) as an output with value high -+ * explicitly since it doesn't have an external pull up. It uses direct -+ * register access because it's called from board_early_init_f(). -+ */ -+ writel(readl(SCU_BASE | SCU_410) & ~SCU_410_RGMII3TXD1, -+ SCU_BASE | SCU_410); -+ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C3, -+ AST_GPIO_BASE | GPIO_004); -+ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C3, -+ AST_GPIO_BASE | GPIO_000); -+} -+ - void espi_init(void); - int arch_interrupt_init_early(void); - -@@ -167,6 +188,8 @@ int board_early_init_f(void) - * I am not sure if it actually does anything... */ - arch_interrupt_init_early(); - -+ disable_crashlog_trigger(); -+ - gpio_passthru_init(); - - port80h_snoop_init(); --- -2.7.4 - diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch index ce9aa668a..66f3d3b12 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch @@ -1,4 +1,4 @@ -From 959b75b846aa25168fe9e3d04ceb0e0778f89992 Mon Sep 17 00:00:00 2001 +From 143fb89b03af61bd807b0d6f9f11d6801cf8fe69 Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Fri, 3 Jan 2020 12:52:29 +0800 Subject: [PATCH] Enable interrupt in u-boot. @@ -15,9 +15,7 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> --- arch/arm/lib/vectors.S | 31 ++++++- board/aspeed/ast2600_intel/ast-irq.c | 154 +++++++++++++++++------------------ - configs/evb-ast2600_defconfig | 1 + - include/configs/evb_ast2600.h | 1 + - 4 files changed, 107 insertions(+), 80 deletions(-) + 2 files changed, 105 insertions(+), 80 deletions(-) diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 2ca6e2494a7a..e2ed04a204de 100644 @@ -432,27 +430,6 @@ index f817f8cd7c81..6e91b17ab186 100644 } } } -diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig -index 517d59adaf11..9cd7aea98e8d 100644 ---- a/configs/evb-ast2600_defconfig -+++ b/configs/evb-ast2600_defconfig -@@ -72,3 +72,4 @@ CONFIG_SPI=y - CONFIG_DM_SPI=y - CONFIG_SYSRESET=y - CONFIG_WDT=y -+CONFIG_USE_IRQ=y -diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h -index 91a42f2522e2..15061b25d872 100644 ---- a/include/configs/evb_ast2600.h -+++ b/include/configs/evb_ast2600.h -@@ -8,6 +8,7 @@ - - #include <configs/aspeed-common.h> - -+#define CONFIG_USE_IRQ - #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000) - #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000) - -- 2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch index ca5846416..34d8b1abb 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch @@ -1,4 +1,4 @@ -From 8c953c7f1d512cf4acd9ce000d65e46094d61597 Mon Sep 17 00:00:00 2001 +From c438edace30a3408c827faaae2d5004fe5ae010d Mon Sep 17 00:00:00 2001 From: arun-pm <arun.p.m@linux.intel.com> Date: Fri, 29 Nov 2019 00:19:09 +0530 Subject: [PATCH] SPI Quad IO Mode @@ -8,13 +8,14 @@ This commit adds quad IO mode in SPI driver for AST2600. Note:- Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode. --- - arch/arm/dts/ast2600-intel.dts | 6 ++--- - drivers/mtd/spi/spi-nor-ids.c | 7 +++++- - drivers/spi/aspeed_spi.c | 46 ++++++++++++++++++++++++---------- - 3 files changed, 41 insertions(+), 18 deletions(-) + arch/arm/dts/ast2600-intel.dts | 6 ++---- + drivers/mtd/spi/spi-nor-ids.c | 7 ++++++- + drivers/spi/aspeed_spi.c | 18 +++++++++++++++++- + 3 files changed, 25 insertions(+), 6 deletions(-) + mode change 100755 => 100644 drivers/spi/aspeed_spi.c diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts -index 0d362ac7c1..2a74bbd30a 100644 +index d16581c5811d..ab78b516b6a3 100644 --- a/arch/arm/dts/ast2600-intel.dts +++ b/arch/arm/dts/ast2600-intel.dts @@ -101,16 +101,14 @@ @@ -37,7 +38,7 @@ index 0d362ac7c1..2a74bbd30a 100644 }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c -index c77987f1ff..d679238562 100644 +index ad733e71988b..257ab472305c 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = { @@ -55,7 +56,9 @@ index c77987f1ff..d679238562 100644 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, #endif diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c -index a8c2b3de2b..ae5edaee9f 100644 +old mode 100755 +new mode 100644 +index c7b998fadfde..930b18443a48 --- a/drivers/spi/aspeed_spi.c +++ b/drivers/spi/aspeed_spi.c @@ -16,6 +16,9 @@ @@ -63,68 +66,12 @@ index a8c2b3de2b..ae5edaee9f 100644 #define ASPEED_SPI_MAX_CS 3 +#define AST2600A0 0x05000303 -+#define AST2600A0_MAX_FREQ 40000000 ++#define AST2600A0_MAX_FREQ 40000000 +#define AST_MAX_FREQ 100000000 struct aspeed_spi_regs { u32 conf; /* 0x00 CE Type Setting */ -@@ -593,6 +596,7 @@ static int aspeed_spi_write_reg(struct aspeed_spi_priv *priv, - aspeed_spi_write_to_ahb(flash->ahb_base, write_buf, len); - aspeed_spi_stop_user(priv, flash); - -+ debug("=== write opcode [%x] ==== \n", opcode); - switch(opcode) { - case SPINOR_OP_EN4B: - writel(readl(&priv->regs->ctrl) | BIT(flash->cs), &priv->regs->ctrl); -@@ -615,6 +619,8 @@ static void aspeed_spi_send_cmd_addr(struct aspeed_spi_priv *priv, - /* First, send the opcode */ - aspeed_spi_write_to_ahb(flash->ahb_base, &cmdbuf[0], 1); - -+ if(flash->iomode == CE_CTRL_IO_QUAD_ADDR_DATA) -+ writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); - /* - * The controller is configured for 4BYTE address mode. Fix - * the address width and send an extra byte if the SPI Flash -@@ -664,9 +670,6 @@ static ssize_t aspeed_spi_write_user(struct aspeed_spi_priv *priv, - { - aspeed_spi_start_user(priv, flash); - -- if(flash->iomode == CE_CTRL_IO_QPI_DATA) -- writel(flash->ce_ctrl_user | flash->iomode, &priv->regs->ce_ctrl[flash->cs]); -- - /* cmd buffer = cmd + addr : normally cmd is use signle mode*/ - aspeed_spi_send_cmd_addr(priv, flash, cmdbuf, cmdlen); - -@@ -872,15 +875,19 @@ static int aspeed_spi_flash_init(struct aspeed_spi_priv *priv, - else - read_hclk = aspeed_spi_hclk_divisor(priv, slave->speed); - -- if (slave->mode & (SPI_RX_DUAL | SPI_TX_DUAL)) { -- debug("CS%u: setting dual data mode\n", flash->cs); -- flash->iomode = CE_CTRL_IO_DUAL_DATA; -- flash->spi->read_opcode = SPINOR_OP_READ_1_1_2; -- } else if (slave->mode & (SPI_RX_QUAD | SPI_TX_QUAD)) { -- flash->iomode = CE_CTRL_IO_QUAD_DATA; -- flash->spi->read_opcode = SPINOR_OP_READ_1_4_4; -- } else { -- debug("normal read \n"); -+ switch(flash->spi->read_opcode) { -+ case SPINOR_OP_READ_1_1_2: -+ case SPINOR_OP_READ_1_1_2_4B: -+ flash->iomode = CE_CTRL_IO_DUAL_DATA; -+ break; -+ case SPINOR_OP_READ_1_1_4: -+ case SPINOR_OP_READ_1_1_4_4B: -+ flash->iomode = CE_CTRL_IO_QUAD_DATA; -+ break; -+ case SPINOR_OP_READ_1_4_4: -+ case SPINOR_OP_READ_1_4_4_4B: -+ flash->iomode = CE_CTRL_IO_QUAD_ADDR_DATA; -+ break; - } - - if(priv->new_ver) { -@@ -986,6 +993,19 @@ static int aspeed_spi_bind(struct udevice *bus) +@@ -1011,6 +1014,19 @@ static int aspeed_spi_bind(struct udevice *bus) return 0; } @@ -144,7 +91,7 @@ index a8c2b3de2b..ae5edaee9f 100644 static int aspeed_spi_probe(struct udevice *bus) { struct resource res_regs, res_ahb; -@@ -1016,7 +1036,7 @@ static int aspeed_spi_probe(struct udevice *bus) +@@ -1041,7 +1057,7 @@ static int aspeed_spi_probe(struct udevice *bus) clk_free(&hclk); priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", @@ -154,5 +101,5 @@ index a8c2b3de2b..ae5edaee9f 100644 priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); -- -2.17.1 +2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch index 94a658610..e8ffb4e72 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch @@ -1,20 +1,31 @@ -From 3f53513c2b16ce2f9a24975cb23b2b58e70ba0f2 Mon Sep 17 00:00:00 2001 +From ddf356e738ab147775bf49a3a4fae179c0dde9ef Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Wed, 29 Jan 2020 14:55:44 -0800 -Subject: [PATCH] Override OTP strap settings +Subject: [PATCH] ast2600: Override OTP strap settings This commit adds settings to override OTP strap. +Also, this commit disables SoC debug interface. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - arch/arm/mach-aspeed/ast2600/platform.S | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) + arch/arm/mach-aspeed/ast2600/platform.S | 26 +++++++++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index 80ba06802acd..e7ae9041093c 100644 +index d107ed80a835..eb3cb2f38cb6 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -147,6 +147,26 @@ do_primary_core_setup: +@@ -45,7 +45,9 @@ + #define AST_SCU_HPLL_PARAM_EXT (AST_SCU_BASE + 0x204) + #define AST_SCU_MFP_CTRL15 (AST_SCU_BASE + 0x454) + #define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) ++#define AST_SCU_HW_STRAP1_CLR (AST_SCU_BASE + 0x504) + #define AST_SCU_HW_STRAP2 (AST_SCU_BASE + 0x510) ++#define AST_SCU_HW_STRAP2_CLR (AST_SCU_BASE + 0x514) + #define AST_SCU_CA7_CTRL (AST_SCU_BASE + 0x800) + #define AST_SCU_CA7_AXI_PREFETCH_START (AST_SCU_BASE + 0x808) + #define AST_SCU_CA7_AXI_PREFETCH_END (AST_SCU_BASE + 0x80C) +@@ -146,6 +148,26 @@ do_primary_core_setup: /* unlock system control unit */ scu_unlock @@ -41,6 +52,27 @@ index 80ba06802acd..e7ae9041093c 100644 /* identify AST2600 A0/A1 */ ldr r0, =AST_SCU_REV_ID ldr r0, [r0] +@@ -241,19 +263,17 @@ wait_lock: + ldr r1, =AST_FMC_CE0_CTRL + str r0, [r1] + +-#if 0 + /* disable UART-based SoC Debug Interface UART5 and P2A bridge*/ + ldr r0, =AST_SCU_DEBUG_CTRL + ldr r1, [r0] + orr r1, #0x03 + str r1, [r0] +- ++ + /* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */ + ldr r0, =AST_SCU_DEBUG_CTRL2 + ldr r1, [r0] + orr r1, #0x0A + str r1, [r0] +-#endif + + /* Strongest LADESPID Driving Strngth */ + ldr r0, =AST_SCU_MFP_CTRL15 -- 2.7.4 diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch new file mode 100644 index 000000000..9af713c99 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch @@ -0,0 +1,60 @@ +From 9d2d9b9db7796a49d03ac8b19dfbdefbe840c506 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Wed, 25 Mar 2020 15:04:26 -0700 +Subject: [PATCH] AST2600: Add TPM pulse trigger + +This commit adds TPM pulse trigger into u-boot booting. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + board/aspeed/ast2600_intel/intel.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index 04fd450d14fc..34b37cc24f91 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -35,6 +35,31 @@ int gpio_abort(void) + return value <= 0 ? 0 : 1; + } + ++/* use GPIOC2 on intel boards */ ++#define TPM_EN_GPIO "gpio@1e78000018" ++ ++int enable_onboard_tpm(void) ++{ ++ struct gpio_desc desc; ++ int ret; ++ ++ ret = dm_gpio_lookup_name(TPM_EN_GPIO, &desc); ++ if (ret) ++ return ret; ++ ret = dm_gpio_request(&desc, "tpm_en_pulse"); ++ if (ret) ++ return ret; ++ if (dm_gpio_is_valid(&desc)) { ++ dm_gpio_set_value(&desc, 1); ++ mdelay(50); ++ dm_gpio_set_value(&desc, 0); ++ printf("TPM: Pulse triggered\n"); ++ } ++ dm_gpio_free(desc.dev, &desc); ++ ++ return ret; ++} ++ + #define SCU_BASE 0x1E6E2000 + #define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK + #define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK +@@ -234,6 +259,8 @@ int board_early_init_r(void) + + espi_init(); + ++ (void) enable_onboard_tpm(); ++ + return 0; + } + +-- +2.7.4 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch index 5522d5f6c..915b0197f 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch @@ -1,4 +1,4 @@ -From ccfc20ceb2931e84ffb02b01099ccb7610b44d9c Mon Sep 17 00:00:00 2001 +From c2e2496dfd8cde56e32274b11968185a77f40736 Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Tue, 10 Dec 2019 14:58:10 +0800 Subject: [PATCH] AST2600: Enable host searial port clock configuration in @@ -14,18 +14,17 @@ by default is 24Mhz. Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> --- - board/aspeed/ast2600_intel/intel.c | 36 ++++++++++++++++++++++++++++++++++++ - 1 file changed, 36 insertions(+) + board/aspeed/ast2600_intel/intel.c | 35 +++++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index 100eb1e..eb6fbaf 100644 +index a02e246d0d81..eb9b3959625e 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -35,9 +35,45 @@ int gpio_abort(void) - return value <= 0 ? 0 : 1; +@@ -36,9 +36,44 @@ int gpio_abort(void) } -+#define SCU_BASE 0x1E6E2000 + #define SCU_BASE 0x1E6E2000 +#define SCU_338 0x338 //Generate UART 24 MHz Reference from UXCLK +#define SCU_33C 0x33c //Generate UART 24 MHz Reference from HUXCLK +#define SCU_338_R_VALUE_192MHZ 0x8e diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch new file mode 100644 index 000000000..1b4201f5e --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch @@ -0,0 +1,36 @@ +From 23e29ce85056f2b296d938e1244b5b2f2160069e Mon Sep 17 00:00:00 2001 +From: Kuiying Wang <kuiying.wang@intel.com> +Date: Wed, 4 Mar 2020 13:21:12 +0800 +Subject: [PATCH] AST2600: PFR u-boot env changes as per PFR BMC image + +u-boot env changes as per PFR BMC flash layout. + +Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> +--- + include/configs/aspeed-common.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h +index 0ece4a1b94..6291e0e7d9 100644 +--- a/include/configs/aspeed-common.h ++++ b/include/configs/aspeed-common.h +@@ -53,13 +53,13 @@ + * Miscellaneous configurable options + */ + #ifndef CONFIG_BOOTCOMMAND +-#define CONFIG_BOOTCOMMAND "bootm 20080000" ++#define CONFIG_BOOTCOMMAND "bootm 20b00000" + #endif + #define CONFIG_SYS_REDUNDAND_ENVIRONMENT + #define CONFIG_ENV_ADDR_REDUND + #define CONFIG_ENV_OVERWRITE + #define AST_FMC_CS0_BASE 0x20000000 /* CS0 */ +-#define CONFIG_ENV_OFFSET 0x2400000 ++#define CONFIG_ENV_OFFSET 0xa0000 + #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET) + #define CONFIG_ENV_SIZE 0x10000 + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +-- +2.20.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch new file mode 100644 index 000000000..3833d2a31 --- /dev/null +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/0043-PFR-Skip-counting-WDT2-event-when-EXTRST-is-set.patch @@ -0,0 +1,45 @@ +From 51ae3c80f20be3b8e010aa57041fa9c38076cc76 Mon Sep 17 00:00:00 2001 +From: Vikram Bodireddy <vikram.bodireddy@intel.com> +Date: Wed, 18 Mar 2020 21:47:11 +0530 +Subject: [PATCH] PFR- Skip counting WDT2 event when EXTRST# is set + +PFR CPLD drives EXTRST# of BMC to reset it during +firmware update and during recovery. On ast2500 the +EXTRST# is also setting WDT2/3 flags which is counted +as boot failures by u-boot and aborts the boot if +boot failures are more than 3. This change will skip +counting WDT2 flag if EXTRST# is also set in SCU3C. + +Tested: Verified BMC updates 4 times and checked that + the boot is not aborted at u-boot. + +Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> +--- + board/aspeed/ast-g5/ast-g5-intel.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c +index 575061ff88..872c7a843a 100644 +--- a/board/aspeed/ast-g5/ast-g5-intel.c ++++ b/board/aspeed/ast-g5/ast-g5-intel.c +@@ -145,6 +145,7 @@ static const GPIOValue gpio_table[] = { + #define HOST_SERIAL_B_HIGH_SPEED (1 << 1) + + #define WATCHDOG_RESET_BIT 0x8 ++#define EXTRST_RESET_BIT 0x2 + #define BOOT_FAILURE_LIMIT 0x3 + + #define BRIGHTON_CITY_BOARD_ID 0 +@@ -572,7 +573,8 @@ void ast_g5_intel_late_init(void) + + boot_failures = get_boot_failures(); + +- if (reset_reason & WATCHDOG_RESET_BIT) ++ if ((reset_reason & WATCHDOG_RESET_BIT) && ++ !(reset_reason & EXTRST_RESET_BIT)) + set_boot_failures(boot_failures + 1); + else + set_boot_failures(0); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg index 8e247744a..99ac5a220 100644 --- a/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg +++ b/meta-openbmc-mods/meta-common/recipes-bsp/u-boot/files/intel.cfg @@ -6,6 +6,22 @@ CONFIG_CMD_LED=y CONFIG_TARGET_AST2600_INTEL=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_DEFAULT_DEVICE_TREE="ast2600-intel" CONFIG_SYS_ARCH_TIMER=y +CONFIG_USE_IRQ=y CONFIG_CMD_IRQ=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x2400000 +CONFIG_BOOTCOMMAND="bootm 20080000" +CONFIG_TARGET_EVB_AST2600A1=n +CONFIG_PHY_NCSI=n +CONFIG_CMD_USB=n +CONFIG_CMD_EXT4=n +CONFIG_CMD_EXT4_WRITE=n +CONFIG_CMD_FAT=n +CONFIG_CMD_FS_GENERIC=n +CONFIG_CMD_MTDPARTS=n +CONFIG_EFI_PARTITION=n +CONFIG_USB=n +CONFIG_DM_USB=n +CONFIG_USB_EHCI_HCD=n +CONFIG_USB_STORAGE=n
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