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From b6bce26bf19e74863e145e6e6e1f6e458077a31a Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Fri, 3 Jan 2020 15:14:09 -0800
Subject: [PATCH] AST2600: Adjust default GPIO settings
- Disable GPIOC3 to prevent unexpected host failures.
- Fixed GPIOC5, GPIOG6, GPIOI0~7 and GPIOL6~7 directions and
default values.
- Disabled internal pull-down of GPIOB6.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
board/aspeed/ast2600_intel/intel.c | 50 ++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
index d1ac8651ac6c..b1a08db91bec 100644
--- a/board/aspeed/ast2600_intel/intel.c
+++ b/board/aspeed/ast2600_intel/intel.c
@@ -162,6 +162,54 @@ static void sgpio_init(void)
SCU_BASE | SCU_414);
}
+#define SCU_410 0x410 /* Multi-function Pin Control #4 */
+#define GPIO_000 0x000 /* GPIO A/B/C/D Value */
+#define GPIO_004 0x004 /* GPIO A/B/C/D Direction */
+#define GPIO_020 0x020 /* GPIO E/F/G/H Value */
+#define GPIO_024 0x024 /* GPIO E/F/G/H Direction */
+#define GPIO_070 0x070 /* GPIO I/J/K/L Value */
+#define GPIO_074 0x074 /* GPIO I/J/K/L Direction */
+
+static void set_gpio_default_state(void)
+{
+#define SCU_410_RGMII3TXD1 BIT(19)
+#define GPIO_C3 BIT(19)
+
+ /*
+ * Set GPIOC3 as an output with value high explicitly since it doesn't
+ * have an external pull up. It uses direct register access because
+ * it's called from board_early_init_f().
+ */
+ writel(readl(SCU_BASE | SCU_410) & ~SCU_410_RGMII3TXD1,
+ SCU_BASE | SCU_410);
+ writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C3,
+ AST_GPIO_BASE | GPIO_004);
+ writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C3,
+ AST_GPIO_BASE | GPIO_000);
+
+#define SCU_610 0x610 /* Disable internal pull-down #0 */
+#define SCU_610_GPIOB6 BIT(14)
+ writel(readl(SCU_BASE | SCU_610) | SCU_610_GPIOB6, SCU_BASE | SCU_610);
+
+ /*
+ * GPIO C5 has a connection between BMC(3.3v) and CPU(1.0v) so if we
+ * set it as an logic high output, it will be clipped by a protection
+ * circuit in the CPU and eventually the signal will be detected as
+ * logic low. So we leave this GPIO as an input so that the signal
+ * can be pulled up by a CPU internal resister. The signal will be
+ * 1.0v logic high resultingy.
+ */
+#define GPIO_C5 BIT(21)
+ writel(readl(AST_GPIO_BASE | GPIO_004) & ~GPIO_C5,
+ AST_GPIO_BASE | GPIO_004);
+
+#define GPIO_G6 BIT(22)
+ writel(readl(AST_GPIO_BASE | GPIO_024) | GPIO_G6,
+ AST_GPIO_BASE | GPIO_024);
+ writel(readl(AST_GPIO_BASE | GPIO_020) | GPIO_G6,
+ AST_GPIO_BASE | GPIO_020);
+}
+
static void timer_handler(void *regs)
{
printf("+");
@@ -175,6 +223,8 @@ int board_early_init_f(void)
* I am not sure if it actually does anything... */
arch_interrupt_init_early();
+ set_gpio_default_state();
+
gpio_passthru_init();
port80h_snoop_init();
--
2.7.4
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