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Changelog:
version 0.3.9 - Nov 29th 2023
=============
- block PLL resetting in secondary boot.
- PLLs are set only after PORST.
(PLLs only, other dividers like FIU are set on any reset).
- Change print of DRAM type.
- Print all values in MHz (instead of Hz).
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I409d725b0e8e93b7e8497a0a20243956ee47571b
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Changelog:
IGPS 03.09.08 - Nov 29th 2023
============
- Write key mask automatically by scripts.
- Bootblock version 0.3.9:
* block PLL resetting in secondary boot.
* PLLs are set only after PORST.
(PLLs only, other dividers like FIU are set on any reset).
* Change print of DRAM type.
* Print all values in MHz (instead of Hz).
- XML:
* XML mark the key_mask area as reserved.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I2e3b552d540006595d761866a4b489506ae2c3e2
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Bingo_0.0.6 - Jul 24th 2023
==============
- For nibble parity- use only option of singular 0xff or 0x00 mask,
no matter what content format it has.
- For secded parity - no more usage of maskAllSizes,
use only option of singular 0xff or 0x00 mask.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I705dce3b342ccff89fd9bd65563fc6d80d907835
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Changelog:
version 0.3.8 - Nov 6th 2023
=============
- bootblock output file rename back to arbel_a35_bootblock.bin.
- unused fuse data moved under ifdef.
- Add 3 fields to header (FIU_DRD_CFG for fiu 0, 1, 3).
User can change these values in IGPS. bootblock does not check value is legal
- Cleanup makefile.
version 0.3.7 - Nov 2nd 2023
=============
- Modify the Makefile to ensure compatibility with Linux compilation
and incorporate a build.sh script.
- In NO_TIP mode: if training fails perform FSW to retry.
- In TIP mode: need to use TIP_FW 0.6.5 and up so that TIP will reset MC
before bootblock to ansure no BMC access during reset MC.
- Update timer driver with registers and basic functunality.
- Update FIU divider on every reset, according to header.
- Set RDLEN to 0 on AHB6 and AHB13.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I581651ed36ef51c01c97312a2be7e438cbc403a5
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Changelog:
TIP_FW: 0.6.5 L0 0.5.4 L1
==============
* MC reset, if needed, performed synchronously
from TIP side while BMC is in reset.
Add new variable SA_TIP_IMAGE for supporing SA TIP_FW mimic no_tip mode.
SA (Stand Alone) is a special TIP_FW for mimic NO TIP feature on TIP devices.
That's concatenated file image_no_tip + SA FW for mimic NO TIP mode.
Tested:
Build pass and boot up successful with correct TIP FW latest version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ib836cf16f0f14f313b5243e18e8d615e792408b5
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Changelog:
IGPS 03.09.07 - Nov 6 2023
============
- Remove Google TIP_FW. SA FW replaces it.
- Bootblock version 0.3.8:
* bootblock output file rename back to arbel_a35_bootblock.bin.
* unused fuse data moved under ifdef
* Add 3 fields to header (FIU_DRD_CFG for fiu 0, 1, 3).
User can change these values in IGPS.
bootblock does not check value is legal.
* Cleanup makefile.
- XML:
* add FIU_DRD_CFG0, 1, 3 to bootblock headers.
IGPS 03.09.06 - Nov 2 2023
============
- TIP_FW: 0.6.5 L0 0.5.4 L1
* MC reset, if needed, performed synchronously from TIP side
while BMC is in reset.
- Bootblock version 0.3.7
* Modify the Makefile to ensure compatibility with Linux
compilation and incorporate a build.sh script.
* In NO_TIP mode: if training fails perform FSW to retry.
* In TIP mode: need to use TIP_FW 0.6.5 and up so that TIP
will reset MC before bootblock to ensure no BMC access.
* during reset MC.
* Update timer driver with registers and basic functionality.
* Update FIU divider on every reset, according to the header.
* Set RDLEN to 0 on AHB6 and AHB13.
- bl31:
* https://github.com/Nuvoton-Israel/arm-trusted-firmware/releases/tag/v2.9.0
* Fix GFX frame buffer memory corruption during secondary boot.
- Scripts:
* create image_no_tip_SA.bin for A1 mimic no_tip mode
(concatenated file image_no_tip + SA FW).
Tested:
Build pass and boot up successful both TIP and NO TIP mode.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ia11b8120b31da4d4da05a9e3034db52a7a17498f
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Brian Ma (1):
spi-nor-ids: Add flash model w25q01jv support
Eason Yang (1):
cmd: fuse: casting u32 to u8 if CONFIG_NPCM
Marvin Lin (1):
cmd: Reset GFX PCI before configuration
Stanley Chu (6):
board: arbel: fix incorrect ram size of 4GB dram with ECC enabled
configs: poleg: update supported baud rate
configs: npcm8xx: disable CONFIG_SPI_FLASH_USE_4K_SECTORS
npcm8xx: support dcache off
serial: npcm: Fix wrong register base address
board: nuvoton: arbel: Fix wrong place to set dram bank size
Tim Lee (1):
i2c: npcm: enable support Fast mode
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I182071fd5dff369f716e483ac34e6bec0bb02f3c
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Changelog:
version 0.3.6 - Oct 19th 2023
=============
- Fix SPIX settings. SPIX should be below 33MHz.
It was calculated according to SPI0 and not SPIX, and then set to SPIX.
- Read the DIE information from OTP and place it in SCRACHPAD 72 and 73,
for the OPTEE to read it.
- Bug fix:
return pass status to TIP in secondary reset if training is skipped.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I6cc76c7750c185f6593da17f779cbd1e68539833
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Changelog:
TIP FW 0.6.4 L0 0.5.3 L1
==============
- Fix DRAM window handling bug, oinorder to allow loading images
to any address in DRAM.
- Fix access for Z1 devices to NCL lib.
- Move tip log to end of recovery flash.
- Support flash encryption. Need to create per die key and enable
in each image header.
- Fix TAG aliign issue.
- Support A35 bootblock reset case.
- Switch to lightweight X.509 and base64 API to remove mbedTLS
from L0 completely.
- Extend key scan option from TIP_ROM to all images.
- Enhance NCL hash porting with SW SHA1 support.
- TIP_SCR0 fix configuration during BMC reset.
- Update OEM table.
- Customize TIP DICE layer 0 to generate ECC-384 device ID
key pair matching ROM.
- Generate counter DICE is missing. Fuse DME and DICE request.
Tested:
Build pass and boot up successful with correct TIP FW latest version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I1c523ee6c1a74439354fda76e6a1abf973f32182
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Changelog:
IGPS 03.09.05 - Oct 23 2023
==============
- OPTEE: 0.0.4:
Reading HUK from UUID stored in two scratchpad registers.
- Add UpdateInputBinaries for A2. Files are the same as A1.
- u-boot: v2023.10-npcm8xx-20231023:
First release of npcm-v2023.10.
Fix memory corruption in GFX frame buffer.
- TIP_FW 0.6.4 L0 0.5.3 L1
Fix DRAM window handling bug, in order to allow loading images
to any address in DRAM.
Fix access for Z1 devices to NCL lib.
Move tip log to end of recovery flash.
Support flash encryption. Need to create per die key and enable
in each image header.
Fix TAG alignment issue.
Support A35 bootblock reset case.
Switch to lightweight X.509 and base64 API to remove mbedTLS from
L0 completely.
Extend key scan option from TIP_ROM to all images.
Enhance NCL hash porting with SW SHA1 support.
TIP_SCR0 fix configuration during BMC reset.
Update OEM table.
Customize TIP DICE layer 0 to generate ECC-384 device ID key pair
matching ROM.
Generate counter DICE is missing. Fuse DME and DICE requests.
- Bootblock 0.3.6:
Fix SPIX settings. SPIX should be below 33MHz.
It was calculated according to SPI0 and not SPIX, and then set to SPIX.
Read the DIE information from OTP and place it in SCRACHPAD 72 and 73,
for the OPTEE to read it.
Bug fix: return pass status to TIP in secondary reset if training is skipped.
Tested:
Build pass and boot up successful both TIP and NO TIP mode.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Id040079d81d3dd77bc57d5857bcd5df930fd503c
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Changelog:
TIP FW 0.6.2 L0 0.5.1 L1
==============
- Release tag: TIP_FW_L0_0.6.2_L1_0.5.1
- Fix trap issue in export found on DC_SCM only.
- Optimize memory usage.
- RSA and RNG code cleanup.
Tested:
Build pass and boot up successful with correct version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ie35d15345fdefbdb9d66801f3ebb70ffc39d776d
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Changelog:
IGPS 03.09.03 - Aug 10th 2023
==============
- Update scripts: fix typos.
- Update scripts: copy all keys always.
To replace a key please remove it from both:
IGPS_..\py_scripts\ImageGeneration\keys
IGPS_..\py_scripts\ImageGeneration\inputs\key_input
Tested:
Build pass and boot up successful both TIP and NO TIP mode.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I4f364735d393d6c84475fd11f96da14e4b1d7b56
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Stanley Chu (7):
pinctrl: npcm8xx: sync with upstream driver
pinctrl: npcm8xx: add name for gpio function
board: nuvoton: set console environment variable
serial: npcm: support skip uart initialization
configs: arbel/poleg: support more uart baud rate
watchdog: npcm: fix reset/expire function
dts: npcm8xx: add watchdog
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Id3923f96f68fa0f59f18b7f6d9f533d48d7cb6b1
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Changelog:
IGPS 02.01.18 - Jul 27th 2023
==============
- BootBlock 10.10.18 Date: 24.07.24
================== ===============
Add support for baud rate setting
supported baud rates 115200, 460800
- Support BAUD Rate configuration (115200, 460800)
- XML: Add baud rate setting to BootblockAndHeader.XML
Default value is 115200.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I93d6b37fdf1d4662cfe84b11dd73d7aa3d24aaf6
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Changelog:
IGPS 03.09.02 - Jul 24th 2023
==============
- bootblock 0.3.5
https://github.com/Nuvoton-Israel/npcm8xx-bootblock/
releases/tag/A35_BootBlock_0.3.5
* bug fix: support NO_TIP mode + updated memory map.
all images are loaded to DRAM. (from version bootblock 0.3.4)
* Call CLK_ConfigureFIUClock only in PORST
(update SPI dividers from header).
* re-enable HOST_IF field in header. Supported values:
0xFF: do nothing
0x00: LPC.
0x01: eSPI
0x02: GPIOs TRIS.
0x03: release host wait, disable eSPI
configuration is done only in PORST.
- add baud rate field to header:
* Supported values: 9600,14400,19200,38400,57600,115200,230400,
380400,460800,921600. Default is 115200.
- Update README with signing options.
- Support pkcs11-tool on Linux.
- Bingo 0.0.6.
https://github.com/Nuvoton-Israel/bingo/releases/tag/Bingo_0.0.6
- update Monitor 1.0.9 (contact Nuvoton for internal users only)
- Optee npcm845x_3.22.0-rc1-7:
https://github.com/Nuvoton-Israel/optee_os/releases/tag/3.22.0-rc1-7
* change load address of OPTEE-OS from 0x36000000 to 0x02100000
* added HUK reading from TIP Mailbox DME PCR0
- TIP_FW 0.6.1 L0 0.5.0 L1:
* Update RCR regs whenever PORST bit is set in TIP_SCR1
(ignore all other bits)
* Export PCI parameters on any reset,
re-order the parameter locations.
* Fix typos un uptime and similar.
* SWRST4 is TIP_RESET.
##uboot https://github.com/Nuvoton-Israel/u-boot/
releases/tag/v2021.04-npcm8xx-20230724
* u-boot.bin is built with extra config to skip
UART initialization in u-boot (CONFIG_SYS_SKIP_UART_INIT=y)
- Update bootblock XML:
* Add host IF field. eSPI in all flavors except Google XML.
* Add BAUD rate field. default is 115200.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ib9d19566ef42d4bbcc3c15df599e396b25e2eede
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We add wks file and relative config for build wic image. Now user can
build wic image by include phosphor-mmc.inc. And set WKS_RWFS_SIZE,
WKS_RWFS_SIZE to adjust eMMC parition size instead of create new wks
file for each board.
Change-Id: I1ed342658d791fd9011bd31ea6db36d4362d120b
Signed-off-by: Brian Ma <chma0@nuvoton.com>
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Update new fw_env.config for U-Boot fw_print/setenv utils access correct
U-Boot environment offset. And also add recipe
udev-nuvoton-mtd-partitions for create readable mtd device symlink.
Change-Id: I3bfa2015f536b27382f561bd8cdb0d7dbd2d88cd
Signed-off-by: Brian Ma <chma0@nuvoton.com>
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For compatible with the newest IGPS 3.9.1 design for new memory map.
Thus, we need to change uboot load address and CONFIG_SYS_MEM_TOP_HIDE.
Stanley Chu (3):
npcm8xx: enable configs for optee/tpm
arbel: change uboot load address
arbel: change CONFIG_SYS_MEM_TOP_HIDE default value
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I498c9f62ae41aa5685f49184420e04572fb64a44
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Changelog:
TIP FW 0.6.0 L0 0.4.9 L1
==============
* New memory map. TIP_VIRTUAL_FLASH_BASE_ADDR moved to 0x1000000.
* Fix NVIC_TrapHandlerCommon: uart reconfig should be after sampling core registers.
* Fix DRAM window handling bug, in order to allow loading images to any address in DRAM.
* In recovery mode: add an option to go to halt (print "N" at the start).
* Add the support for enforcing recovery image to match active at boot time
* Add support for ECC 384 + 521
* Add the support of ecc HW with tip_ecc_hw_ncl.c instead of old implementation using mbedtls code
* Wake all 4 cores when jump to DRAM (feature was limited to RAM2 only).
* Bug fix SFDP dummy byte.
Tested:
buid pass and boot up successful with correct TIP FW latest version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I0d848f329a7954ca0b65644d368de93296b6e822
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Changelog:
version 0.3.4 - Jun 26th 2023
=============
- Bug fix: support NO_TIP mode + new memory map.
All images are loaded to DRAM.
version 0.3.3 - Jun 18th 2023
=============
- Add header field GMMAP at offset 0x152 which is copied
to INTCR4.GMMAP0 and 1.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I711d377f3c4c7da1b106cef8e6e8f8b7824f10f1
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Changelog:
IGPS 03.09.01 - Jun 26th 2023
==============
- TIP FW 0.6.0 L0 0.4.9 L1
* New memory map. TIP_VIRTUAL_FLASH_BASE_ADDR moved to 0x1000000.
* Fix NVIC_TrapHandlerCommon: uart reconfig should be after
sampling
core registers.
* Fix DRAM window handling bug, in order to allow loading images to
any address in DRAM.
* In recovery mode: add an option to go to halt
(print "N" at the start).
* Add the support for enforcing recovery image to match
active at boot time
* Add support for ECC 384 + 521
* Add the support of ecc HW with tip_ecc_hw_ncl.c instead of old
implementation using mbedtls code
* Wake all 4 cores when jump to DRAM
(feature was limited to RAM2 only).
* Bug fix SFDP dummy byte.
- Remove no_tip file from ReplaceComponent.bat
- uboot:
New memory map.
- bl31: Release V2.8.2
* change load address of BL31 to 0x02000000
* change load address of OPTEE-OS to 0x02100000
* change load address of BL33 to 0x06208000
- optee: Release npcm845x_3.18.0_v1.0-697
* change load address of OPTEE-OS from to 0x02100000
- bootblock 0.3.3
* Add header field GMMAP at offset 0x152 which is copied to
INTCR4.GMMAP0 and 1.
- XML: add bootblock field to select GMMAP. Default is zero.
If it's FF value is set as before by bootblock, according to DRAM
size.
- XML: bootblock sets MC to 1050MHz by default.
- Bug fix in Open_all_ports batch.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I7ae7eb915530397e1a1a3f26a766e208e02c25c1
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Jim Liu (4):
clk: npcm7xx: fix bug for calculate pll clock
pinctrl: npcm: add reset type detect
npcm8xx: fix reset reason issue for bootup
npcm8xx: Add PORST detect and remove workaround
Joseph Liu (1):
dts: nuvoton-npcm845: eanble ftpm and optee support
Judy Wang (1):
drivers:optee:rpmb: initialize drivers of mmc devices in UCLASS_BLK for rpmb access
Marvin Lin (2):
dts: nuvoton-npcm845: enable RMII1 pins
board: nuvoton: arbel: Correct CONFIG_SYS_MEM_TOP_HIDE value
Stanley Chu (19):
npcm_otp: correct the return value of fuse read
npcm845-evb: configure rgmii2 phy voltage by dts
npcm845-evb: set spix frequency to 50MHz
dts: nuvoton-npcm845: set default uart clock rate
dts: npcm8xx: add fm0 pinctrl
misc: npcm_host_intf: change initialization sequence
spi: npcm_fiu: do not change fiu clock
clk: nuvoton: npcm8xx: set ahb/apb/fiu clock divider as read-only
Revert "npcm845-evb: set spix frequency to 50MHz"
spi: npcm_pspi: use ACTIVE_LOW flag for cs gpio and set default max_hz
npcm845-evb: support TPM spi device
arbel: add CONFIG_EXT_TPM2_SPI for external tpm2 device
phy: add dt-bindig for npcm usb phy
npcm8xx: support 4Gb ram
gpio: npcm: set output state before enabling the output
spi: npcm_pspi: update dts and debug log
npcm_otp: read fuse bytes with byte offset
arbel: update configs
npcm8xx: add A2 CPU version
Tim Lee (3):
tools: env: use /run to store lockfile
drivers: spi: fix compiler warnings from npcm_fiu_spi_probe
configs: arbel: enable CONFIG_SPI_FLASH_GOOGLE
Tyrone Ting (1):
dts: nuvoton-npcm845: enable FIU3 voltage configuration
Change-Id: I178cfe008b962a48ff1a6b3eb8a0c80d1f0fd34a
Signed-off-by: Brian Ma <chma0@nuvoton.com>
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Add sign images feature according customer's requirement.
Set "SECURED_IMAGE" to "True" and enable sign images feature.
When sign images feature be enabled. Use default keys to sign
images if customer didn't point their own local keys path.
Note: "SECURED_IMAGE" default is "True".
Tested:
Use default keys sign:
That will use default path and keys from igps to sign.
Use local keys sign:
That will use local path and keys to sign.
When KEY_FOLDER and KEY definition both are valid.
However, when KEY_FOLDER and KEY definition are invalid either,
that will output sign images failed then stop build full images.
Tested: build pass and boot up successfully with signed
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: If2b793906ab338aec391062d9bfeae2b1e790078
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Changelog:
IGPS 03.09.00 - May 18th 2023
==============
- TIP_FW 0.5.9 L0 0.4.8 L1
- Bootblock version 0.3.2
- skip clearing INTCR2
- SCRPAD 10 is now reset
- split CRC file (tip\notip)
- Clear SCRPAD10-19
- Add BootBlockAndHeader_A1_EB_NoTip.xml for EB
IGPS 03.08.09 - May 14th 2023
==============
- TIP_FW 0.5.9 L0 0.4.8 L1
- Bootblock version 0.3.1
- Added code for A2
- flash: support flash size mix
- restore: force main and recovery flashes to the same
- Add timestamp compare to combo
IGPS 03.08.08 - May 3rd 2023
==============
- TIP_FW 0.5.7 L0 0.4.6 L1
- Bootblock version 0.3.0
- Added support for no TIP mode
- No TIP mode is only for A2 users
- IGPS still supports TIP mode
IGPS 03.08.07 - April 17th 2023
==============
- TIP_FW 0.5.7 L0 0.4.6 L1
- Bootblock version 0.2.9
- Support A2
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I2a2902f0ba07ad2ab2002357c8e5a4a228ed311a
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npcm8xx-tip-fw already specifies IGPS_MACHINE configuration.
Thus, remove npcm8xx-tip-fw_0.4.5.0.3.4-GOOGLE2.bb in this layer.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I81b1e3d6088e3cb14e4f5392d866c689062556d3
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In a base bb file where we are setting the primary git repository, it
is rare that we need to `SRC_URI +=`. This is an unnecessary pattern
that seems to have been copied throughout the repository. Remove the
pattern where appropriate and simply set SRC_URI directly.
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: I430186a82f9582ba6196f5bf66b659af4092b48d
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Changelog:
IGPS 03.08.06 - Mar 2nd 2023
==============
- TIP_FW 0.5.6 L0 0.4.5 L1
* Avoid forcing sig check on BMC images.
- Add support for RemoteHSM
IGPS 03.08.05 - Feb 7th 2023
==============
- bl31: npcm845x_2.6.0_1.5-1-g69e6d531f.
- TIP_FW 0.5.5 L0 0.4.4 L1
* tip_mbx: reconfig the uart after BMC is up (singleton).
* recovery: warn the user and give them curtesy 10 seconds.
* bug fix: flash: wrong init fiu and cs in xfer.
* bug fix: flash: support single flash mode. tested on 4MB and 16MB.
IGPS 03.08.04 - Jan 16th 2023
==============
- TIP_FW 0.5.4 L0 0.4.3 L1
* bmc_reset: if BMC init fails reset the TIP.
* reinitialized the SPI in case Linux changed settings of flash.
* update reset indication: bug fix handle only in PORST.
* print reset type in bmc reset too.
* in secondary reset clear RESSR and TIP_SCR1 and update INTCR2
to show only latest reset.
- TIP FW 0.5.4 L0 0.4.3 L1 GOOGLE5, derived from version mentioned above.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ie694976d74f35af1deb44c14d1db4234a390e932
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Changelog:
TIP_FW 0.5.6 L0 0.4.5 L1
==============
* Avoid forcing sig check on BMC images
TIP_FW 0.5.5 L0 0.4.4 L1
==============
* tip_mbx: reconfig the uart after BMC is up (singleton).
* recovery: warn the user and give them curtesy 10 seconds.
* bug fix: flash: wrong init fiu and cs in xfer.
* bug fix: flash: support single flash mode. tested on 4MB and 16MB.
TIP_FW 0.5.4 L0 0.4.3 L1
==============
* bmc_reset: if BMC init fails reset the TIP.
* reinitialized the SPI in case Linux changed settings of flash.
* update reset indication: bug fix handle only in PORST.
* print reset type in bmc reset too.
* in secondary reset clear RESSR and TIP_SCR1 and update INTCR2
to show only latest reset.
TIP FW 0.5.4 L0 0.4.3 L1 GOOGLE5
==============
* derived from TIP FW 0.5.4 L0 0.4.3 L1.
Tested:
buid pass and boot up successful with correct TIP FW latest version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I6a84525d18c85e789075baf741002df8f15e1837
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Change to use TIPFW binary file from git repository directly that
make recipe more clearer to maintain in the future upgrade.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Icc413ced0ea3f92f9866647b11642a1191853082
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Change to use the LICENSE file from git repository to avoid
build warning/error when fetch this package at the first time.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I84e01df1413308e87c61149225738d54b44b8169
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Changelog:
TIP_FW_L0_0.5.3_L1_0.4.2
==============
- TIP_FW L0 version 0.5.3 and L1 version 0.4.2 L1
- FreeRTOS: in case of assert: print useful info.
- NVIC_BMC_reset: clear NVIC int before reloading BMC.
- in BMC reset and spurious interrupt reset: read the int number from
the active and not the pending.
- NVIC_IntHandlerCommon: bug fix: clear correct number.
- Big fix: enable all traps in hardware_app_init.
- Add task bmc_task to handle BMC reset reload.
- Increase heap_size to 0xA000.
- HOSTPER: set to 1 till KCS bug is fixed.
- Flash: check if FIU1 and FIU 0\CS1 are disabled by OTP bit.
- Flash: bug fix: do not enable FIU1 CS2\3.
- Flash: Allow using a 4MB flash for image.
- Update FreeRTOS to none-MPU version.
- Spurious interrupt handling: in case of spurious interrupt print
correct int number + NVIC state, and then clear it.
- OTP version: use two bits for each version number.
- Copy DBGRST too to INTCR2.
- Debug log: bug fix: data corruption in case of a 16MB flash. Replace
the code so that Debug log is 64KB (one flash block). its location is
- split flash for active recovery: 64KB before recovery image.
- two flash mode: last block in active flash.
- UUID: add full data read (wafer, X\Y, year, work week). Note: debug
chips do not contain this info.
TIP FW 0.5.1 L0 0.4.0 L1
==============
- Set RCR regs only in PORST.
- Change RCR values for TIP reset.
- NVIC: print more data on spurious interrupts.
- SPIX - set FIU_FIX to SINGLES. Other FIUs remain in INCREASING mode as
before.
TIP FW 0.5.1 L0 0.4.0 L1 GOOGLE4
==============
- derived from TIP FW 0.5.1 L0 0.4.0 L1
Tested:
buid pass and boot up successful with correct TIP FW latest version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I2b5093470d6caa2e26bb287ec7dda3a8d0c4404c
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Changelog:
IGPS 03.08.03 - Jan 9th 2023
==============
- TIP_FW 0.5.3 L0 0.4.2 L1
- FreeRTOS: in case of assert: print useful info.
- NVIC_BMC_reset: clear NVIC int before reloading BMC.
- in BMC reset and spurious interrupt reset: read the int number from
the active and not the pending.
- NVIC_IntHandlerCommon: bug fix: clear correct number.
- Big fix: enable all traps in hardware_app_init.
- Add task bmc_task to handle BMC reset reload.
- Increase heap_size to 0xA000.
- HOSTPER: set to 1 till KCS bug is fixed.
- Flash: check if FIU1 and FIU 0\CS1 are disabled by OTP bit.
- Flash: bug fix: do not enable FIU1 CS2\3.
- Flash: Allow using a 4MB flash for image.
- Update FreeRTOS to none-MPU version.
- Spurious interrupt handling: in case of spurious interrupt print
correct int number + NVIC state, and then clear it.
- OTP version: use two bits for each version number.
- Copy DBGRST too to INTCR2.
- Debug log: bug fix: data corruption in case of a 16MB flash. Replace
the code so that Debug log is 64KB (one flash block). its location is
- split flash for active recovery: 64KB before recovery image.
- two flash mode: last block in active flash.
- UUID: add full data read (wafer, X\Y, year, work week). Note: debug
chips do not contain this info.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ie2d5086127da69f94d7b5cbe55ed89b1e6e49f30
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Changelog:
- Add flag CERBERUS_SECURE_BOOT_ONLY. No udpate, recovery and logging.
Change-Id: Id242eca001cadd7e6a0ed116300baa87f56a0ddb
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
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Also remove Google-specific version since it has been merged into the
mainline branch.
Changelog:
IGPS 03.08.00 - Dec 15th 2022
==============
- TIP_FW: 0.5.0 L0 0.3.9 L1
- Code cleanup for production.
- bug fix key selection during recovery.
- Add DME+RIOT data export to PCI MBOX.
- align BMC and TIP that both will use PLL2 and not CLKREF.
- Bug fix: don't save previous INTCR2 for reset indication.
- Bug fix: update flow using wrong KMT.
- TIP_FW: 0.5.0 L0 0.3.9 L1 GOOGLE3
- aligned to the above release.
- split SFDP
- enable flag CERBERUS_SECURE_BOOT_ONLY
- uboot https://github.com/Nuvoton-Israel/u-boot/releases/tag/v2021.04-npcm8xx-20221215
- OpTee: https://github.com/Nuvoton-Israel/optee_os/releases/tag/npcm845x_3.18.0_v1.0
- linux offset 4MB.
- Update scripts to sign in yocto build (signatures only).
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: I396a8e05bc6aa53fd6c7062ed342ce1f26b7e2fb
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Changelog:
version 0.2.8 - Nov 22 2022
=============
- Bug fix: disable RECALIB in DDR, after training, before sweep phase.
- eSPI: enable auto handshake.
Version 0.2.6 - Oct 26 2022
=============
- Bug fix: If DRAM is 2GB and max DRAM size in header is smaller, GMMAP
should be set according to header, not according to the physical
device.
Version 0.2.4 - Oct 18 2022
=============
- MC: Support 2GB DRAM
- MC: Updated TRFC default to 2GB DRAM and fixed value for 1600/1G
- CLK: always set PLLs by bootblock. Set all dividers in PORST.
- SPI-X: upper limit of 33MHz.
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: Ia82fba195139d245ccb7f62218a900069c575e2c
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Follow the other npcm8xx recipes to use different versions of this
recipe for different platforms.
Tested: build pass and boot up successfully with correct bootblock
version.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ic97de46876e7e821b65515846d40c939d273bcc1
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IGPS 03.07.03 - Oct 12 2022
==============
- U-boot 2021.04-npcm8xx-20221011
- TIP_FW 0.4.6 L0 0.3.5 L1
- Support all board types (flash connections detected at runtime)
- Bootblock XML: return FIU to 50MHz in bootblock header
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I2bf9fe80c8d66d83109d8aa67c0461f828abfef0
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Joseph Fu (1):
dts: npcm730 GBS: update uboot dts for npcm-v2021.04
Joseph Liu (1):
configs: arbel: update uimage_flash_addr to 0x80400000
Stanley Chu (7):
env: Support ENV offset behind the U-boot image
env: print env offset if uboot pointer is enabled
configs: arbel: add defconfig for enabling uboot_pointer feature
spi: npcm_fiu: support spix
dts: nuvoton-npcm845-evb: enable spix
configs: npcm8xx: change env offset
configs: arbel: change ramdisk load address
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I44ca7bb622ceb721400f3ce14254de7545c6bc35
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The `{A,B}` expansion syntax is a bash extension which isn't supported
on some other shells.
Tested: Built successfully with non-bash shell
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: Iae3168e0699d0e399b0f1dcfbd978dcc16aadbf5
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These versions of IGPS and the TIP FW have customizations for Google.
Other users of npcm8xx can add customized or pinned versions here too as
necessary.
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: I14001205636fd9697f7953594c3d02ad58b398a1
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This method is less likely to break and require fixes when Nuvoton
adjusts the XML files.
Tested: Still able to build successfully
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: Ib8e67b67cd837d1d5510ab326012d0644b3a2780
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This will allow us to use different versions of this recipe for
different platforms.
Tested: No impact to the resulting recipe
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: I90cf725589c5df48d17668bf8afe3ef3db7d8e2e
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This will allow us to use different versions of this recipe for
different platforms.
Tested: No impact to the resulting recipe
Signed-off-by: Benjamin Fair <benjaminfair@google.com>
Change-Id: I5a4e58d0a013ab5ac3df5ff47f02c8004ead6249
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- TIP_FW L0 version 0.4.6 and L1 version 0.3.5 L1
- Support all board types (flash connections detected at runtime)
- To be used in IGPS 3.7.3 and above
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ic4a4e74bb266a0d106af483047cda261dd94788e
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https://gerrit.openbmc.org/c/openbmc/openbmc/+/55099 added npcm8xx-igps
together with a patch, and later npcm8xx-igps SRCREV was bumped in
https://gerrit.openbmc.org/c/openbmc/openbmc/+/57109, but the patch was
not refreshed. This would cause fuzz detected.
Change-Id: Iaeaf5aa8091b347039ed4cfa187e252e60660f00
Signed-off-by: Anthony <anthonyhkf@google.com>
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Version 0.2.3 - Sep 20 2022:
1. MC: set bit 8 for DLL reset after writing to MRS registers.
2. Flash: remove scan for uboot.
3. Remove FIU driver (not used).
Tested: build pass and boot up successful
>================================================
> Arbel A35 BootBlock by Nuvoton Technology Corp. Ver 0.2.3
>================================================
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I271318595382795153b24e646bdd56d087e1eabc
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Upgrade IGPS from 03.06.02 to 03.06.04 and remove duplicate deploy
Previous npcm8xx-ipgs recipe will deploy BB and TIPFW binary.
However, BB and TIPFW recipes already were merged recently.
They will do their own deploy task individually.
Thus, we should remove duplicate deploy in igps recipe.
IGPS 03.06.04 - Aug 14 2022
==============
- TIP_FW 0.4.1 L0 0.2.6 L1
* flash driver bug fixes.
* Core reset bug fix: CORSTC: set to 1s, except MC bit
* Do not continue if BMC fail to boot.
* RESSR: copy values from TIP_SCR1 to INTCR2. Print last reset type.
* OEM: read 2 bytes from OTP (was 1).
- Bootblock is alligned to 512KB.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Id0b7336f0b2ada9e43385d635f3e3536a70aad8d
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The Arbel NPCM8XX requires a TIP FW image which handles various security tasks.
Releases/TIP_FW_L0_0.4.1_L1_0.2.6 version:
1. Flash driver bug fixes.
2. Bug fix CS1 slew rate.
3. Print all SFDP info.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I54c0c7b46972b7a261c5d8c73472ae57c2346fb7
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The Arbel NPCM8XX requires a bootblock image that will initiate
the DRAM and basic HW settings.
First release constrains only binaries. Version is A35_BootBlock_0.2.2
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ia5904dca98c44df8ed4c2af6f599965ccfd4aec2
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IGPS 03.06.02 - Jul 24 2022
==============
- Restore Z1 XMLs.
- Bug fix ReplaceComponent.bat
- Add fiu clk dividers fields to Bootblock header xml.
- TIP FW: 0.3.9 L0 0.2.4 L1:
- virtual flash bug fix: use memcy instead of tip_memcpy.
- shared attestation hash is 512.
- tip_mbx bug fixes.
- tip_combo: return early if failed to find image.
- init WD0RCR, 2, 3 before BMC starts.
- check load and verify return status. if verify tip images fail in secure boot, restart.
- Bootblock: 0.2.2
- Fix GMMAP value for 2GB and 512MB.
- Add 3 FIU dividers to the the header (require IGPS 3.6.2 and above)
- Bug fix: add support for ODT termination of zero (termination disabled).
- Print pass\fail criteria for sweeps. Need to enable debug prints to use.
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ibd19031adf33d6a6ec5ada905490ba50c92e1948
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