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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-14 15:49:03 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-17 22:25:35 +0300 |
| commit | ee8ce199c7017123b8f2d20f03bfa93351db399b (patch) | |
| tree | 8ff218eb7950917f40fc5f3dad9e0ab6bf986a3f /arch/arm64/boot/dts/renesas/r8a779g0.dtsi | |
| parent | 5bb355a8d62383b1cbc244897bf6c95724ffbf6e (diff) | |
| download | linux-ee8ce199c7017123b8f2d20f03bfa93351db399b.tar.xz | |
arm64: dts: renesas: r8a779g0: Add CPU core clocks
Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/r8a779g0.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 21baa4936b4f..9cbe337220ed 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -46,6 +46,7 @@ next-level-cache = <&L3_CA76_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; }; a76_1: cpu@100 { @@ -56,6 +57,7 @@ next-level-cache = <&L3_CA76_0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; }; a76_2: cpu@10000 { @@ -66,6 +68,7 @@ next-level-cache = <&L3_CA76_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; }; a76_3: cpu@10100 { @@ -76,6 +79,7 @@ next-level-cache = <&L3_CA76_1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; }; idle-states { |