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authorDinh Nguyen <dinguyen@kernel.org>2021-03-03 00:41:50 +0300
committerStephen Boyd <sboyd@kernel.org>2021-03-31 05:26:26 +0300
commit8c489216c3e103a24856fd676fc5f51619c2e052 (patch)
treed18847f00d12685742da45529ff5325c269d6172 /drivers/clk/socfpga/clk-gate-a10.c
parent2c2b9c6067170de2a63e7e3d9f5bb205b870de7c (diff)
downloadlinux-8c489216c3e103a24856fd676fc5f51619c2e052.tar.xz
clk: socfpga: arria10: convert to use clk_hw
As recommended by Stephen Boyd, convert the Arria10 clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/socfpga/clk-gate-a10.c')
-rw-r--r--drivers/clk/socfpga/clk-gate-a10.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index cd5df9103614..f5cba8298712 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -98,7 +98,7 @@ static void __init __socfpga_gate_init(struct device_node *node,
u32 div_reg[3];
u32 clk_phase[2];
u32 fixed_div;
- struct clk *clk;
+ struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
@@ -159,13 +159,13 @@ static void __init __socfpga_gate_init(struct device_node *node,
init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
init.parent_names = parent_name;
socfpga_clk->hw.hw.init = &init;
+ hw_clk = &socfpga_clk->hw.hw;
- clk = clk_register(NULL, &socfpga_clk->hw.hw);
- if (WARN_ON(IS_ERR(clk))) {
+ if (clk_hw_register(NULL, hw_clk)) {
kfree(socfpga_clk);
return;
}
- rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+ rc = of_clk_add_provider(node, of_clk_src_simple_get, hw_clk);
if (WARN_ON(rc))
return;
}