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2023-06-09arm64: tegra: Enable thermal support on Jetson AGX OrinThierry Reding3-5/+45
Add thermal zone details and enable the PWM fan as cooling device. Note that this also changes the cooling levels for the PWM fan, which should have no effect, though, because the fan wasn't previously connected to anything and by default would be turned off at probe time. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add Tegra234 thermal supportThierry Reding1-0/+53
Add device tree node for the BPMP thermal node on Tegra234 and add thermal zone definitions. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add a few blank lines for better readabilityThierry Reding1-0/+10
Surround device tree nodes with blank lines for increased readability. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Sort properties more logicallyThierry Reding1-2/+1
We typically sort the "compatible" property first because it defines what the remainder of the properties can be. For the sound node on the Jetson AGX Orin this wasn't done, so fix that up. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Enable GPU on SmaugDiogo Ivo1-0/+5
Enable the GPU on the Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-09arm64: tegra: Add GPU power rail regulator on SmaugDiogo Ivo1-1/+17
Add the GPU power rail regulator node for the Pixel C. Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Update USB phy-name for Jetson Orin NXJon Hunter1-1/+1
Running 'make dtbs_check' reports the following warning for the Jetson Orin NX platform ... arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dtb: usb@3550000: phy-names:1: 'usb3-0' was expected Fix this by updating the phy-names:1 to be 'usb3-0' as expected. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Enable USB device for Jetson AGX OrinJon Hunter1-1/+10
Enable USB device support for the Jetson AGX Orin platform and update the mode for the usb2-0 port to be on-the-go. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Add Tegra234 pin controllersPrathamesh Shete1-0/+12
Add the device tree nodes for the MAIN and AON pin controllers found on the Tegra234 family of SoCs. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-06arm64: tegra: Support Jetson Orin Nano Developer KitThierry Reding3-0/+29
The NVIDIA Jetson Orin Nano Developer Kit is the combination of the NVIDIA Jetson Orin Nano (P3767, SKU 5) module and the P3768 carrier board. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-06-01arm64: tegra: Add missing cache properties on Tegra210Krzysztof Kozlowski1-0/+1
As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: tegra210-p2371-0000.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-26arm64: tegra: Fix PCIe regulator for Orin Jetson AGXJon Hunter1-1/+1
The PCIe slot on the Jetson Orin AGX is not working and PCIe cards are not detected. The regulator for the 3.3V regulator for the PCIe is using the wrong GPIO for turning on the regulator. Fix this by updating the 3.3V regulator to use the correct GPIO. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-16arm64: tegra: Add CPU OPP tables and interconnects propertySumit Gupta1-0/+276
Add OPP table and interconnects property to scale DDR frequency with CPU frequency for better performance. Each operating point entry of the OPP table has CPU freq to per MC channel bandwidth mapping. One table is added for each cluster even though the table data is same because the bandwidth request is per cluster. This is done because OPP framework creates a single icc path and hence single bandwidth request if the table is marked as 'opp-shared' and shared among all clusters. For us, the OPP table data is same but the MC Client ID argument to interconnects property is different for each cluster. So, having per cluster table makes different icc path for each cluster and helps to make per cluster BW requests. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-16arm64: tegra: Add support for IGX OrinShubhi Garg4-0/+404
Add support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-05-03Merge tag 'for-6.4-rc1' of ↵Linus Torvalds1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux Pull hardware timestamp engine updates from Dipen Patel: "The changes for the hte subsystem include: - Add Tegra234 HTE provider and relevant DT bindings - Update MAINTAINERS file for the HTE subsystem" * tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux: hte: tegra-194: Use proper includes hte: Use device_match_of_node() hte: tegra-194: Fix off by one in tegra_hte_map_to_line_id() hte: tegra: fix 'struct of_device_id' build error hte: Use of_property_present() for testing DT property presence gpio: tegra186: Add Tegra234 hte support hte: handle nvidia,gpio-controller property hte: Deprecate nvidia,slices property hte: Add Tegra234 provider hte: Re-phrase tegra API document arm64: tegra: Add Tegra234 GTE nodes dt-bindings: timestamp: Deprecate nvidia,slices property dt-bindings: timestamp: Add Tegra234 support MAINTAINERS: Add HTE/timestamp subsystem details
2023-04-27arm64: tegra: Add Tegra234 GTE nodesDipen Patel1-0/+17
Add GTE LIC and AON GPIO nodes for the tegra234 SoC. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2023-04-25Merge tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds12-25/+708
Pull ARM SoC devicetree updates from Arnd Bergmann: "The devicetree changes overall are again dominated by the Qualcomm Snapdragon platform that weighs in at over 300 changesets, but there are many updates across other platforms as well, notably Mediatek, NXP, Rockchips, Renesas, TI, Samsung and ST Microelectronics. These all add new features for existing machines, as well as new machines and SoCs. The newly added SoCs are: - Allwinner T113-s, an Cortex-A7 based variant of the RISC-V based D1 chip. - StarFive JH7110, a RISC-V SoC based on the Sifive U74 core like its JH7100 predecessor, but with additional CPU cores and a GPU. - Apple M2 as used in current Macbook Air/Pro and Mac Mini gets added, with comparable support as its M1 predecessor. - Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC - Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs, based on the Cortex-A53 and Cortex-A73 cores, respectively. - Qualcomm sa8775p is an automotive SoC derived from the Snapdragon family. Including the initial board support for the added SoC platforms, there are 52 new machines. The largest group are 19 boards industrial embedded boards based on the NXP i.MX6 (32-bit) and i.MX8 (64-bit) families. Others include: - Two boards based on the Allwinner f1c200s ultra-low-cost chip - Three 'Banana Pi' variants based on the Amlogic g12b (A311D, S922X) SoC. - The Gl.Inet mv1000 router based on Marvell Armada 3720 - A Wifi/LTE Dongle based on Qualcomm msm8916 - Two robotics boards based on Qualcomm QRB chips - Three Snapdragon based phones made by Xiaomi - Five developments boards based on various Rockchip SoCs, including the rk3588s-khadas-edge2 and a few NanoPi models - The AM625 Beagleplay industrial SBC Another 14 machines get removed: both boards for the obsolete 'oxnas' platform, three boards for the Renesas r8a77950 SoC that were only for pre-production chips, and various chromebook models based on the Qualcomm Sc7180 'trogdor' design that were never part of products" * tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (836 commits) arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b arm64: dts: apple: t8112: Add PWM controller arm64: dts: apple: t600x: Add PWM controller arm64: dts: apple: t8103: Add PWM controller arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x ARM: dts: nomadik: Replace deprecated spi-gpio properties ARM: dts: aspeed-g6: Add UDMA node ARM: dts: aspeed: greatlakes: add mctp device ARM: dts: aspeed: greatlakes: Add gpio names ARM: dts: aspeed: p10bmc: Change power supply info arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer arm64: dts: mediatek: mt6795: Add tertiary PWM node arm64: dts: rockchip: add panel to Anbernic RG353 series dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC dt-bindings: arm: fsl: Add chargebyte Tarragon dt-bindings: vendor-prefixes: add chargebyte ...
2023-04-05arm64: tegra: Add vccmq on Jetson TX2Ben Dooks1-0/+1
The TX2 SoM's SDIO WiFI card is connected via mmc@3440000 however it does not look like the upstream kernel is even bothering to power this (and the regulator framework shuts down this power rail post kernel init). The issue seems to be a missing link for vccq from the MAX77620 PMIC's LDO5 which is labeled vddio_sdmmc3 (and not used anywhere else) to the mmc@3440000 node to ensure there is at leasr bus power. Note this does not fix the WiFi issue on upstream kernels, there is still something else missing that gets the BCM WiFi device to detect properly. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-05arm64: tegra: Populate USB Type-C Controller for Jetson AGX OrinJon Hunter1-0/+78
Add the USB Type-C controller that is present on the Jetson AGX Orin board. The ports for the Type-C controller are not populated yet, but will be added later once the USB host and device support for Jetson AGX Orin is enabled. This is based upon a patch from Wayne Chang <waynec@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-04arm64: tegra: Audio codec support on Jetson AGX OrinSameer Pujar1-1/+44
Jetson AGX Orin has onboard RT5640 audio codec. This patch adds the codec device node and the bindings to I2S1 interface. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-04arm64: tegra: Support Jetson Orin NX reference platformThierry Reding3-0/+381
Add support for the combination of the NVIDIA Jetson Orin NX (P3767, SKU 0) module and the P3768 carrier board. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-04arm64: tegra: Support Jetson Orin NXThierry Reding2-0/+186
This adds a device tree for the Jetson Orin NX module, which is Jetson AGX Orin's little sibling with 6 or 8 ARM Cortex-A78AE cores, an Ampere GPU (1024 GPU and 32 tensor cores) and a number of accelerators for machine learning, image processing and more. The Jetson Orin NX comes with either 8 or 16 GiB of 128-bit LPDDR5 and supports NVME for mass storage. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-03arm64: tegra: Add DSU PMUs for Tegra234Jon Hunter1-0/+18
Populate the DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) devices for Tegra234 which has one DSU PMU per CPU cluster. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-03arm64: tegra: Drop serial clock-names and reset-namesKrzysztof Kozlowski5-24/+0
The serial node does not use clock-names and reset-names: tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-03-02arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234Thierry Reding2-2/+2
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map, so bump the CBB ranges property to cover all of the 1 TiB address space. This fixes an issue where some of the PCIe regions could not be remapped because of they were outside the memory specified by the CBB's ranges property. Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-27arm64: tegra: Drop I2C iommus and dma-coherent propertiesThierry Reding3-48/+0
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that represent the GPC DMA controller, since that is the device performing the direct memory accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-26arm64: tegra: Mark host1x as dma-coherent on Tegra194/234Mikko Perttunen2-0/+2
Ensure appropriate configuration is done to make the host1x device and context devices DMA coherent by adding the dma-coherent flag. Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-24arm64: tegra: Populate the XUDC node for Tegra234Jon Hunter1-0/+23
Populate the Tegra XUSB device controller (XUDC) node for Tegra234. This is based upon a patch from Wayne Chang <waynec@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-24arm64: tegra: Add dma-coherent property for Tegra194 XUDCJon Hunter1-0/+1
DMA operations for XUSB device controller (XUDC) are coherent for Tegra194 and so add the 'dma-coherent' property for this device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Populate Jetson AGX Orin EEPROMsJon Hunter2-0/+48
Populate the module and system EEPROMs on the Jetson AGX Orin platform. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Populate address/size cells for Tegra234 I2CJon Hunter1-0/+16
Populate the address and size cells properties for the I2C devices on Tegra234. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Enable XUSB host function on Jetson AGX OrinWayne Chang3-0/+278
This commit enables XUSB host and pad controller on Jetson AGX Orin. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Sort nodes by unit-address, then alphabeticallyThierry Reding22-6575/+6581
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first. These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance"). While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Bump #address-cells and #size-cellsThierry Reding5-1445/+1453
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space. Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus. Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children. While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Sort includesThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Fix duplicate regulator on Jetson TX1Thierry Reding1-1/+1
When the top-level regulators were renamed, the 1.2V camera regulator accidentally ended up with the same DT node name as the 1.8V camera regulator. Fixes: 097e01c61015 ("arm64: tegra: Rename top-level regulators") Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Fix typo in gpio-ranges propertyThierry Reding1-1/+1
The gpio-ranges property name was missing a terminating "s", causing it to not be parsed and fail DT validation as well. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unneeded clock-names for Tegra132 PWMThierry Reding1-1/+0
There's only a single clock for this IP block, so it doesn't need a clock-names property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234Thierry Reding1-1/+1
The compatible string list for SDHCI on Tegra234 should be "nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci" fallback. Use that consistently for all SDHCI controllers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unused reset-names for QSPIThierry Reding2-3/+0
The Tegra QSPI controller uses a single reset line, so there's no need for a reset-names property. Remove such properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fixup pinmux node namesThierry Reding5-13/+19
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove reset-names for QSPIThierry Reding1-2/+0
The Tegra QSPI controllers use a single reset control, so reset-names is not necessary and therefore not specified in the DT bindings. Drop the property from device tree files to avoid validation warnings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use correct compatible string for Tegra234 HDAThierry Reding1-1/+1
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use correct compatible string for Tegra194 HDAThierry Reding1-1/+1
The Tegra194 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use vbus-gpios propertyThierry Reding1-2/+2
Instead of using the deprecated vbus-gpio property, switch to using the more standard vbus-gpios property. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Restructure Tegra210 PMC pinmux nodesThierry Reding1-21/+19
The PMC pinmux configuration nodes need to be part of a top-level pinmux node. Add that new "pinmux" node and move the configuration nodes into it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update cache propertiesPierre Gondois3-0/+49
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove 'enable-active-low'Fabio Estevam1-1/+0
The 'enable-active-low' property is not a valid one. Only 'enable-active-high' is valid, and when this property is absent the gpio regulator will act as active low by default. Remove the invalid 'enable-active-low' property. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add dma-channel-mask in GPCDMA nodeAkhil R3-3/+9
Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controllerVidya Sagar1-1/+1
Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-27 00:18:21 +0300