summaryrefslogtreecommitdiff
path: root/arch/riscv/errata/sifive/errata.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-29riscv: Avoid TLB flush loops when affected by SiFive CIP-1200Samuel Holland1-0/+5
2023-04-29RISC-V: fix sifive and thead section mismatches in errataRandy Dunlap1-5/+3
2023-04-29Merge tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-4/+4
2023-03-15riscv: alternatives: Rename errata_id to patch_idAndrew Jones1-3/+3
2023-03-15riscv: alternatives: Remove unnecessary define and unused structAndrew Jones1-1/+1
2023-03-07RISC-V: fix taking the text_mutex twice during sifive errata patchingConor Dooley1-1/+1
2023-02-22RISC-V: take text_mutex during alternative patchingConor Dooley1-0/+3
2023-02-01riscv: switch to relative alternative entriesJisheng Zhang1-1/+2
2022-07-08riscv: don't warn for sifive erratas in modulesHeiko Stuebner1-1/+2
2022-05-12riscv: add memory-type errata for T-HeadHeiko Stuebner1-1/+6
2022-05-12riscv: implement module alternativesHeiko Stuebner1-5/+9
2022-05-12riscv: allow different stages with alternativesHeiko Stuebner1-1/+2
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen1-0/+18
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen1-0/+20
2021-04-26riscv: sifive: Add SiFive alternative portsVincent Chen1-0/+68