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path: root/drivers/clk/mediatek/clk-pll.c
AgeCommit message (Expand)AuthorFilesLines
2022-11-29clk: mediatek: Export PLL operations symbolsJohnson Wang1-50/+34
2022-05-20clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai1-17/+18
2022-05-20clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-12/+11
2022-05-19clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen1-8/+4
2022-02-17clk: mediatek: Warn if clk IDs are duplicatedChen-Yu Tsai1-0/+6
2022-02-17clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai1-4/+19
2022-02-17clk: mediatek: pll: Clean up included headersChen-Yu Tsai1-5/+7
2022-02-17clk: mediatek: pll: Implement unregister APIChen-Yu Tsai1-0/+55
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-0/+1
2022-02-17clk: mediatek: Use %pe to print errorsChen-Yu Tsai1-2/+1
2021-09-15clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen1-0/+4
2021-09-15clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen1-1/+1
2021-07-27clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen1-5/+10
2021-07-27clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen1-4/+16
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-04-11clk: mediatek: Allow changing PLL rate when it is offJames Liao1-11/+2
2019-04-11clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu1-6/+11
2019-04-11clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen1-4/+11
2019-04-11clk: mediatek: Disable tuner_en before change PLL rateOwen Chen1-14/+34
2017-11-02clk: mediatek: add the option for determining PLL source clockChen Zhong1-1/+4
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com1-2/+11
2016-11-09clk: mediatek: Add MT2701 clock supportShunli Wang1-0/+1
2016-08-19clk: mediatek: remove __init from clk registration functionsJames Liao1-1/+1
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-6/+1
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao1-3/+15
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao1-2/+2
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao1-9/+12
2015-05-20clk: mediatek: Initialize clk_init_dataRicky Liang1-1/+1
2015-05-06clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao1-0/+332