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author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-22 21:53:37 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-22 21:53:37 +0300 |
commit | 13e574b4941ee1931f8c70f33c3011f74e5fbd30 (patch) | |
tree | 786e3febef35e2db314f96547d04d261733c4f05 /Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml | |
parent | 0175ec3a28c695562a08fdccf73f2ec5ed744e2f (diff) | |
parent | de82c25dab9ac0fa01c95b8914bde8d9ce528e93 (diff) | |
download | linux-13e574b4941ee1931f8c70f33c3011f74e5fbd30.tar.xz |
Merge tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"This has been a fairly quiet release for SPI, though it is likely that
the next release will have some big changes as there's some
preparatory work for multiple chip select support gone in - the rest
of the code is on the list but will need to be rebased onto -rc1.
Otherwise there's a couple of new tunables for chip select timings,
some new devices and smaller device specific updates and fixes.
- Support for configuring the hold and minimum inactive times for
chip selects.
- Beginnings of support for supporting devices which have multiple
chip selects on a single device.
- Support for newer Broadcom HSSPI and Intel controllers, Silicon
Labs EM3581 and SI3210"
* tag 'spi-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (67 commits)
spi: dt-bindings: qcom,spi-qcom-qspi: document OPP and power-domains
spi: spidev: drop the incorrect notice from Kconfig
spi: bcm63xx-hsspi: fix error code in probe
spi: bcmbca-hsspi: Fix error code in probe() function
spi: synquacer: Fix timeout handling in synquacer_spi_transfer_one()
spi: intel: Check number of chip selects after reading the descriptor
spi: xilinx: add force_irq for QSPI mode
spi: spi-st-ssc: convert to DT schema
spi: Reorder fields in 'struct spi_transfer'
spi: cadence-quadspi: use STIG mode for small reads
spi: cadence-quadspi: setup ADDR Bits in cmd reads
spi: cadence-quadspi: Add flag for direct mode writes
spi: cadence-quadspi: Reset CMD_CTRL Reg on cmd r/w completion
MAINTAINERS: Remove file reference for Broadcom Broadband SoC HS SPI driver entry
spi: bcm63xx-hsspi: bcmbca-hsspi: fix _be16 type usage
MAINTAINERS: Add entry for Broadcom Broadband SoC HS SPI drivers
spi: bcmbca-hsspi: Add driver for newer HSSPI controller
spi: bcm63xx-hsspi: Disable spi mem dual io read op support
spi: spi-mem: Allow controller supporting mem_ops without exec_op
spi: bcm63xx-hsspi: Add prepend mode support
...
Diffstat (limited to 'Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml | 134 |
1 files changed, 134 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml new file mode 100644 index 000000000000..6554978583f8 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Broadband SoC High Speed SPI controller + +maintainers: + - William Zhang <william.zhang@broadcom.com> + - Kursad Oney <kursad.oney@broadcom.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0 + controller was carried over to recent ARM based chips, such as BCM63138, + BCM4908 and BCM6858. The old MIPS based chip should continue to use the + brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to + use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as + defined below to match the specific chip along with ip revision info. + + This rev 1.0 controller has a limitation that can not keep the chip select line + active between the SPI transfers within the same SPI message. This can + terminate the transaction to some SPI devices prematurely. The issue can be + worked around by either the controller's prepend mode or using the dummy chip + select workaround. Driver automatically picks the suitable mode based on + transfer type so it is transparent to the user. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller rev 1.1 that add the capability to allow the driver to control chip + select explicitly. This solves the issue in the old controller. + +properties: + compatible: + oneOf: + - const: brcm,bcm6328-hsspi + - items: + - enum: + - brcm,bcm47622-hsspi + - brcm,bcm4908-hsspi + - brcm,bcm63138-hsspi + - brcm,bcm63146-hsspi + - brcm,bcm63148-hsspi + - brcm,bcm63158-hsspi + - brcm,bcm63178-hsspi + - brcm,bcm6846-hsspi + - brcm,bcm6856-hsspi + - brcm,bcm6858-hsspi + - brcm,bcm6878-hsspi + - const: brcm,bcmbca-hsspi-v1.0 + - items: + - enum: + - brcm,bcm4912-hsspi + - brcm,bcm6756-hsspi + - brcm,bcm6813-hsspi + - brcm,bcm6855-hsspi + - const: brcm,bcmbca-hsspi-v1.1 + + reg: + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl + minItems: 1 + + clocks: + items: + - description: SPI master reference clock + - description: SPI master pll clock + + clock-names: + items: + - const: hsspi + - const: pll + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi-v1.0 + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + required: + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + spi@ff801000 { + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; |