diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 14:27:15 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-27 04:27:43 +0300 |
| commit | 1e229c21a47241626b345c31ba443490372cf2b5 (patch) | |
| tree | 4f77303d5ca1dd2808987319f326876ead60cc33 /drivers/clk/at91/sama7g5.c | |
| parent | 0ef99f8202c5078a72c05af76bfaed2ea4daab19 (diff) | |
| download | linux-1e229c21a47241626b345c31ba443490372cf2b5.tar.xz | |
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
one fractional part and one divider. On SAMA7G5 the CPU PLL could be
changed at run-time to implement DVFS. The hardware clock tree on
SAMA7G5 for CPU PLL is as follows:
+---- div1 ----------------> cpuck
|
FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
The div1 block is not implemented in Linux; on prescaler block it has
been discovered a bug on some scenarios and will be removed from Linux
in next commits. Thus, the final clock tree that will be used in Linux
will be as follows:
+-----------> cpuck
|
FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
It has been proposed in [1] to not introduce a new CPUFreq driver but
to overload the proper clock drivers with proper operation such that
cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
clock notifiers which applies safe dividers before FRAC PLL is changed.
The current commit treats only the DIV PLL by adding a notifier that
sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
provided by initialization clock code (sama7g5.c). The div0 is treated
in next commits (to keep the changes as clean as possible).
[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/sama7g5.c')
| -rw-r--r-- | drivers/clk/at91/sama7g5.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 970135e19a75..ae52c10af040 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -127,6 +127,8 @@ static const struct clk_pll_characteristics pll_characteristics = { * @t: clock type * @f: clock flags * @eid: export index in sama7g5->chws[] array + * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE + * notification */ static const struct { const char *n; @@ -136,6 +138,7 @@ static const struct { unsigned long f; u8 t; u8 eid; + u8 safe_div; } sama7g5_plls[][PLL_ID_MAX] = { [PLL_ID_CPU] = { { .n = "cpupll_fracck", @@ -156,7 +159,12 @@ static const struct { .t = PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled. */ .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .eid = PMC_CPUPLL, }, + .eid = PMC_CPUPLL, + /* + * Safe div=15 should be safe even for switching b/w 1GHz and + * 90MHz (frac pll might go up to 1.2GHz). + */ + .safe_div = 15, }, }, [PLL_ID_SYS] = { @@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(struct device_node *np) sama7g5_plls[i][j].p, i, sama7g5_plls[i][j].c, sama7g5_plls[i][j].l, - sama7g5_plls[i][j].f); + sama7g5_plls[i][j].f, + sama7g5_plls[i][j].safe_div); break; default: |