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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-27 20:57:01 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-07-22 03:19:24 +0300 |
| commit | 1b58b4cac6fc6fab55f34f74087594125fc60b84 (patch) | |
| tree | 6b6685df5d82ea9e32c130945e23c2d91982b27a /drivers/cxl/cxl.h | |
| parent | de516b40116e98c60ee475e92108453686098c85 (diff) | |
| download | linux-1b58b4cac6fc6fab55f34f74087594125fc60b84.tar.xz | |
cxl/port: Record parent dport when adding ports
At the time that cxl_port instances are being created, cache the dport
from the parent port that points to this new child port. This will be
useful for region provisioning when walking the tree to calculate
decoder targets, and saves rewalking the dport list after the fact to
build this information.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220624041950.559155-1-dan.j.williams@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxl.h')
| -rw-r--r-- | drivers/cxl/cxl.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 326283f1e328..4bdc47600f9d 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -332,6 +332,7 @@ struct cxl_nvdimm { * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders * @endpoints: cxl_ep instances, endpoints that are a descendant of this port + * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @component_reg_phys: component register capability base address (optional) @@ -347,6 +348,7 @@ struct cxl_port { int id; struct list_head dports; struct list_head endpoints; + struct cxl_dport *parent_dport; struct ida decoder_ida; int hdm_end; resource_size_t component_reg_phys; @@ -406,11 +408,12 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport, struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, resource_size_t component_reg_phys, - struct cxl_port *parent_port); + struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct device *dev); int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); int cxl_bus_rescan(void); -struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd); +struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, + struct cxl_dport **dport); bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, |