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2023-03-30arm64: dts: ti: k3-j784s4-evm: Add eMMC mmc0 supportApurva Nandan1-0/+9
Add support for eMMC connected to main sdhci0 instance. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Bhavya Kapoor <b-kapoor@ti.com> Link: https://lore.kernel.org/r/20230327083100.12587-1-a-nandan@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Enable audio on SK-AM62(-LP)Jai Luthra3-0/+95
Add nodes for audio codec and sound card, enable the audio serializer (McASP1) under use from SK-AM62 E2 [1] onwards and update pinmux. Keep all audio related nodes in the common dtsi as they are exactly the same between SK-AM62 and SK-AM62-LP [2]. Link: https://www.ti.com/lit/zip/sprr448 [1] Link: https://www.ti.com/lit/zip/sprr471 [2] Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-2-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am62-main: Add McASP nodesJayesh Choudhary1-0/+60
Add the nodes for McASP 0-2. Use the audio-friendly 96MHz main_1_hsdivout6_clk as clock parent instead of the default 100Mhz main_2_hsdivout8_clk source. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-1-94332149657a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j784s4: Add MCSPI nodesVaishnav Achath2-0/+121
J784S4 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-5-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721s2: Add MCSPI nodesVaishnav Achath2-0/+121
J721S2 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j7200: Add MCSPI nodesVaishnav Achath2-0/+121
J7200 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Keerthy <j-keerthy@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-j721e: Add MCSPI nodesVaishnav Achath2-0/+121
J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: ti: dts: Add support for AM62x LP SKAnand Gadiyar2-0/+228
The AM62x LP SK board is similar to the AM62x SK board, but has some not-so-minor changes that requires different device tree. The differences are mainly: - AM62x SoC in the AMC package that meets AECQ100 automotive standard. - LPDDR4 versus DDR4 on the AM62x SK. - TPS65219 PMIC instead of discrete regulators. - IO expander pin names are wired differently. - Second ethernet port is currently disabled as the boards do not have the part physically installed. - OSPI NAND vs OSPI NOR. - No WLAN chip instead a SDIO M.2 connector. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> [vigneshr@ti.com: Add PMIC node] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-3-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Refractor AM625 SK dtsAnand Gadiyar2-237/+276
To prepare for upcoming derivative boards based on the AM625 SK, refactor the dts file for this board into a common dtsi file that the derivative boards will inherit and retain only those parts that are different in the current dts file. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-2-0a56e1694804@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am625-sk: Add ti,vbus-divider property to usbss1Dhruva Gole1-0/+1
The property "ti,vbus-divider" is needed for both usbss0 and usbss1 as both USB0 and USB1 have the same external voltage divider circuit. Fixes: 2d94dfc43885 ("arm64: dts: ti: k3-am625-sk: Add support for USB") Signed-off-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230328124315.123778-2-rogerq@kernel.org Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: k3-am68-sk-base-board: Update IO EXP GPIO lines for Rev E2Sinthu Raja1-7/+5
Rev E2 of the AM68 SK baseboard has updated the GPIO IO expander pins functionality. To match the Rev E2 schematics, update existing IO expander GPIO line names and the corresponding node which uses the expansion(exp1) node. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Link: https://lore.kernel.org/r/20230315120934.16954-1-sinthu.raja@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-30arm64: dts: ti: Add k3-am625-beagleplayRobert Nelson2-0/+759
BeagleBoard.org BeaglePlay is an easy to use, affordable open source hardware single board computer based on the Texas Instruments AM625 SoC that allows you to create connected devices that work even at long distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L. Expansion is provided over open standards based mikroBUS, Grove and QWIIC headers among other interfaces. This board family can be identified by the 24c32 eeprom: [aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|] [50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|] https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230316152143.2438928-3-nm@ti.com Co-developed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII modeSiddharth Vadapalli2-1/+103
The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: j7200-main: Add CPSW5G nodesSiddharth Vadapalli1-0/+88
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external ports and 1 host port, referred to as CPSW5G. Add device-tree nodes for CPSW5G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII modeSiddharth Vadapalli2-1/+135
The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e: Add CPSW9G nodesSiddharth Vadapalli2-0/+117
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2GSiddharth Vadapalli1-0/+50
Add device tree support to enable MCU CPSW with J784S4 EVM. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230315042548.1500528-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-common-proc-board: Add pinmux information for ADCBhavya Kapoor1-0/+44
J721s2 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62: Add watchdog nodesJulien Panis3-0/+67
Add nodes for watchdogs : - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Julien Panis <jpanis@baylibre.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62-wakeup: Introduce RTC nodeNishanth Menon1-0/+10
Introduce digital RTC node in wakeup domain. Even though this has no specific battery backup supply, this on-chip RTC is used in cost-optimized board designs as a wakeup source. Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230320165123.80561-2-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodesBhavya Kapoor1-0/+40
J721s2 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230316095146.498999-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j784s4-main: Enable crypto acceleratorJayesh Choudhary1-0/+19
Add the node for SA2UL to support hardware crypto algorithms, including SHA-1/256/512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230314152611.140969-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: Use local header for pinctrl register valuesNishanth Menon9-8/+69
The DTS uses hardware register values directly in pin controller pin configuration and not an abstraction of any form. These definitions were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. Store the constants in a header next to DTS and use them instead of bindings. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Suggested-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/c4d53e9c-dac0-8ccc-dc86-faada324beba@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-3-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-j721e-sk: Remove firmware-name override for R5FAndrew Davis1-4/+0
The firmware name for this core should stay as the default name "j7-main-r5f0_0-fw". This is expected to by a symlink to the actual firmware file. If one wants to use a different firmware they should change where the symlink points. This is usually achieved with an update-alternative or other distro specific selection mechanisms. The actual selection is policy and does not belong in DT. Remove this name override. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230307180942.2719-1-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KBVignesh Raghavendra1-1/+1
Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-20arm64: dts: ti: k3-am625: Correct L2 cache size to 512KBVignesh Raghavendra1-1/+1
Per AM62x SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am625 Page 1. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2023-03-14arm64: dts: ti: k3-j784s4-*: Add 'ti,sci-dev-id' for NAVSS nodesJayesh Choudhary2-0/+2
TISCI device ID for main_navss and mcu_navss nodes are missing in the device tree. Add them. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com> Link: https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com
2023-03-14arm64: dts: ti: k3-j721e-main: Remove ti,strobe-sel propertyBhavya Kapoor1-1/+0
According to latest errata of J721e [1], (i2024) 'MMCSD: Peripherals Do Not Support HS400' which applies to MMCSD0 subsystem. Speed modes supported has been already updated but missed dropping 'ti,strobe-sel' property which is only required by HS400 speed mode. Thus, drop 'ti,strobe-sel' property from kernel dtsi for J721e SoC. [1] https://www.ti.com/lit/er/sprz455/sprz455.pdf Fixes: eb8f6194e807 ("arm64: dts: ti: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems") Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Diwakar Dhyani <d-dhyani@ti.com> Reviewed-by: Nitin Yadav <n-yadav@ti.com> Link: https://lore.kernel.org/r/20230203073724.29529-1-b-kapoor@ti.com
2023-03-14arm64: dts: ti: k3-am62a7-sk: Fix DDR size to full 4GBDevarsh Thakkar1-2/+3
All revisions of AM62A7-SK board have 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B memory. Commit 38c4a08c820c ("arm64: dts: ti: Add support for AM62A7-SK") enabled just 2GB due to a schematics error in early revision of the board. Fix it by enabling full 4GB available on the platform. Design docs: https://www.ti.com/lit/zip/sprr459 Fixes: 38c4a08c820c ("arm64: dts: ti: Add support for AM62A7-SK") Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230314094645.3411599-1-devarsht@ti.com
2023-03-14arm64: dts: ti: k3-am62-main: Fix GPIO numbers in DTNitin Yadav1-2/+2
Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according to AM62x SK datasheet. The Link of datasheet is in the following line: https://www.ti.com/lit/ds/symlink/am625.pdf?ts=1673852494660 Section: 6.3.10 GPIO (Page No. 63-67) Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Nitin Yadav <n-yadav@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20230202085917.3044567-1-n-yadav@ti.com
2023-02-01arm64: dts: ti: Makefile: Rearrange entries alphabeticallyVignesh Raghavendra1-13/+23
Entries are first grouped as per SoC present on the board. Groups are sorted alphabetically. This makes it easy to know SoC to board mapping and also add new entries in alphabetical order. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230126071159.2337584-1-vigneshr@ti.com
2023-02-01arch: arm64: dts: Add support for AM69 Starter KitDasnavis Sabiya2-0/+181
AM69 Starter Kit is a single board designed for TI AM69 SOC that provides advanced system integration in automotive ADAS applications, autonomous mobile robot and edge AI applications. The SOC comprises of Cortex-A72s in dual clusters, lockstep capable dual Cortex-R5F MCUs, Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Depth and Motion Processing Accelerators (DMPAC), Deep-learning Matrix Multiply Accelerator(MMA) and C7x floating point vector DSP AM69 SK supports the following interfaces: * 32 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x3 USB 3.0 Type-A ports * x1 USB 3.0 Type-C port * x1 UHS-1 capable micro-SD card slot * x4 MCAN instances * 32 GB eMMC Flash * 512 Mbit OSPI flash * x2 Display connectors * x1 PCIe M.2 M Key * x1 PCIe M.2 E Key * x1 4L PCIe Card Slot * x3 CSI2 Camera interface * 40-pin Raspberry Pi header Add initial support for the AM69 SK board. Design Files: https://www.ti.com/lit/zip/SPRR466 TRM: https://www.ti.com/lit/zip/spruj52 Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119132958.124435-3-sabiya.d@ti.com
2023-01-26arm64: dts: ti: iot2050: Add support for M.2 variantchao zeng2-0/+124
The M.2 variant comes with 2 slots, one B-keyed and another one E-keyed. They are configured by the firmware during startup. Also the device tree will be adjusted according to the detect or manually configured interface mode by the firmware. The kernel only carries a single configuration as base device tree. It has to be built with a symbols node so that the firmware can apply overlays for the connector modes. Signed-off-by: chao zeng <chao.zeng@siemens.com> [Jan: refactored to a single DT] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/878e3a023767b5a6d9d2cff09015678aaba13fce.1674110442.git.jan.kiszka@siemens.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-01-26arm64: dts: ti: iot2050: Add layout of OSPI flashJan Kiszka1-0/+46
Describe the layout of the OSPI flash as the latest firmware uses it. Specifically the location of the U-Boot envs is important for userspace in order to access it. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/d135b246bd302060175276d3653f2891077eb109.1674110442.git.jan.kiszka@siemens.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-01-22arm64: dts: ti: k3-j7200: Fix wakeup pinmux rangeVaishnav Achath2-2/+29
The WKUP_PADCONFIG register region in J7200 has multiple non-addressable regions, split the existing wkup_pmx region as follows to avoid the non-addressable regions and include all valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230119042622.22310-1-vaishnav.a@ti.com
2023-01-22arm64: dts: ti: k3-am68-sk: Add support for AM68 SK base boardSinthu Raja2-0/+337
The SK architecture comprises of baseboard and a SOM board. The AM68 Starter Kit's baseboard contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the base board. Therefore, add support for peripherals brought out in the base board. Schematics: https://www.ti.com/lit/zip/SPRR463 Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230116071446.28867-4-sinthu.raja@ti.com
2023-01-22arm64: dts: ti: Add initial support for AM68 SK System on ModuleSinthu Raja1-0/+29
AM68 Starter Kit (SK) is a low cost, small form factor board designed for TI’s AM68 SoC. TI’s AM68 SoC comprises of dual core A72, high performance vision accelerators, hardware accelerators, latest C71x DSP, high bandwidth real-time IPs for capture and display. The SoC is power optimized to provide best in class performance for industrial applications. AM68 SK supports the following interfaces: * 16 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.1 Type-C port * x2 USB 3.1 Type-A ports * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header SK's System on Module (SoM) contains the SoC and DDR. Therefore, add DT node for the SOC and DDR on the SoM. Schematics: https://www.ti.com/lit/zip/SPRR463 TRM: http://www.ti.com/lit/pdf/spruj28 Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Tested-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230116071446.28867-3-sinthu.raja@ti.com
2023-01-16arm64: dts: Update cache properties for tiPierre Gondois7-0/+8
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com
2023-01-16arm64: dts: ti: Add support for phyBOARD-Electra-AM642Wadim Egorov3-0/+509
Add basic support for phyCORE-AM64x SoM & phyBOARD-Electra-AM642 CB. The phyCORE-AM64x [1] is a SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family. A development Kit, called phyBOARD-Electra [2] is used as a carrier board reference design around the AM64x SoM. Supported features: * Debug UART * Heartbeat LED * GPIO buttons & LEDs * SPI NOR flash * eMMC * CAN * Ethernet * Micro SD card * I2C EEPROM * I2C RTC * I2C LED Dimmer * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am64x [2] Product page CB: https://www.phytec.com/product/phyboard-am64x Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230104162927.1215033-2-w.egorov@phytec.de
2023-01-16arm64: dts: ti: k3-am62a7-sk: Enable USB1 nodeVignesh Raghavendra1-0/+16
Enable USB1 host port on AM62A7 SK. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Acked-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-5-vigneshr@ti.com
2023-01-16arm64: dts: ti: k3-am62a7-sk: Enable ethernet portVignesh Raghavendra1-0/+54
AM62A7 SK has a DP83867 PHY on the board connected to first port of CPSW, enable the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-4-vigneshr@ti.com
2023-01-16arm64: dts: ti: k3-am62a-main: Add more peripheral nodesVignesh Raghavendra1-0/+365
Add DT nodes for main domain SPI, PWM, DMA, CPSW (ethernet), mailbox, spinlock, USB and CAN. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-3-vigneshr@ti.com
2023-01-16arm64: dts: ti: k3-am62a-mcu: Add MCU domain peripheralsVignesh Raghavendra1-0/+51
Introduce DT nodes for MCU domain SPIs and GPIO modules. Co-developed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103042110.1092122-2-vigneshr@ti.com
2023-01-16arm64: dts: ti: Add support for J784S4 EVM boardApurva Nandan2-0/+198
J784S4 EVM board is designed for TI J784S4 SoC. It supports the following interfaces: * 32 GB DDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode * x1 Input Audio Jack, x1 Output Audio Jack * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port * x2 4L PCIe connector * x1 UHS-1 capable micro-SD card slot * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash, UFS flash. * x6 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector * x1 15-pin CSI header * x6 MCAN instances Add basic support for J784S4-EVM. Schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Tested-by: Manorit Chawdhry <m-chawdhry@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-5-a-nandan@ti.com
2023-01-16arm64: dts: ti: Add initial support for J784S4 SoCApurva Nandan3-0/+1605
The J784S4 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive, ADAS and industrial applications requiring AI at the network edge. This SoC extends the K3 Jacinto 7 family of SoCs with focus on raising performance and integration while providing interfaces, memory architecture and compute performance for multi-sensor, high concurrency applications. Some highlights of this SoC are: * Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs, 4 C7x floating point vector DSPs with Matrix Multiply Accelerator (MMA) for deep learning and CNN. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one DPI interface. * Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, Up to 20 MCANs, among other peripherals. See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022) for further details: http://www.ti.com/lit/zip/spruj52 Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-4-a-nandan@ti.com
2023-01-15arm64: dts: ti: k3-am625-sk: Add support for USBAswath Govindraju1-0/+27
AM62 SoC has two instances of USB and they are brought on to the board in the following way, -> USB0 instance - This is brought out to a USB TypeC connector on board through TPS6598 PD controller. The PD controller should decide the role based on CC pin in the connector. Unfortunately the irq line for the TPS isn't hooked up which is a mode not yet support by the driver (some patches were submitted earlier this year[0]). So for now the PD controller is left out and peripheral mode chosen. -> USB1 instance - This is brought out to a USB TypeA connector on board. Therefore, add the required device tree support for the above in the board dts file. 0: https://lore.kernel.org/lkml/f714ee55-ef47-317d-81b9-57020dda064b@ti.com/T/ Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-4-sjoerd@collabora.com
2023-01-15arm64: dts: ti: k3-am62-main: Add support for USBAswath Govindraju1-0/+46
AM62 SoC has two instances of USB on it. Therefore, add support for the same. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-3-sjoerd@collabora.com
2023-01-15arm64: dts: ti: k3-am62-main: Update OTAP and ITAP delay selectNitin Yadav1-22/+24
UHS Class U1 sd-card are not getting detected due to incorrect OTAP/ITAP delay select values in linux. Update OTAP and ITAP delay select values for various speed modes. For sdhci0, update OTAP delay values for ddr52 & HS200 and add ITAP delay for legacy & mmc-hs. For sdhci1 & sdhci2, update OTAP & ITAP delay select recommended as in RIOT for various speed modes. Signed-off-by: Nitin Yadav <n-yadav@ti.com> [cherry-pick from vendor BSP] Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Tested-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112162847.973869-2-sjoerd@collabora.com
2023-01-15arm64: dts: ti: k3-am62-main: Fix clocks for McSPIDhruva Gole1-3/+3
Fixes the clock Device ID's in the DT according to the tisci docs clock identifiers for AM62x Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230103054840.1133711-1-d-gole@ti.com
2022-12-13Merge tag 'pm-6.2-rc1' of ↵Linus Torvalds2-0/+60
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management updates from Rafael Wysocki: "These include two new drivers (cpufreq driver for Apple SoC CPU P-states and the SCMI Powercap based power capping driver), other new hardware support and driver extensions (Qualcomm cpufreq driver and its DT bindings, TI cpufreq driver, intel_pstate, intel-uncore-freq), a bunch of fixes and cleanups all over and a cpupower utility update including new features related to RAPL support. Specifics: - Fix nasty and hard to debug race condition introduced by mistake in the runtime PM core code and clean up that code somewhat on top of the fix (Rafael Wysocki) - Generalize of_perf_domain_get_sharing_cpumask phandle format (Hector Martin) - Add new cpufreq driver for Apple SoC CPU P-states (Hector Martin) - Update Qualcomm cpufreq driver (Manivannan Sadhasivam, Chen Hui): - CPU clock provider support - Generic cleanups or reorganization - Potential memleak fix - Fix of the return value of cpufreq_driver->get() - Update Qualcomm cpufreq driver's DT bindings (Manivannan Sadhasivam, Rob Herring, Melody Olvera): - Support for CPU clock provider - Missing cache-related properties fixes - Support for QDU1000/QRU1000 - Add support for ti,am625 SoC and enable build of ti-cpufreq for ARCH_K3 (Dave Gerlach, and Vibhore Vardhan) - Use flexible array to simplify memory allocation in the tegra186 cpufreq driver (Christophe JAILLET) - Convert cpufreq statistics code to use sysfs_emit_at() (ye xingchen) - Allow intel_pstate to use no-HWP mode on Sapphire Rapids (Giovanni Gherdovich) - Add missing pci_dev_put() to the amd_freq_sensitivity cpufreq driver (Xiongfeng Wang) - Initialize the kobj_unregister completion before calling kobject_init_and_add() in the cpufreq core code (Yongqiang Liu) - Defer setting boost MSRs in the ACPI cpufreq driver (Stuart Hayes, Nathan Chancellor) - Make intel_pstate accept initial EPP value of 0x80 (Srinivas Pandruvada) - Make read-only array sys_clk_src in the SPEAr cpufreq driver static (Colin Ian King) - Make array speeds in the longhaul cpufreq driver static (Colin Ian King) - Use str_enabled_disabled() helper in the ACPI cpufreq driver (Andy Shevchenko) - Drop a reference to CVS from cpufreq documentation (Conghui Wang) - Improve kernel messages printed by the PSCI cpuidle driver (Ulf Hansson) - Make the DT cpuidle driver return the correct number of parsed idle states, clean it up and clarify a comment in it (Ulf Hansson) - Modify the tasks freezing code to avoid using pr_cont() and refine an error message printed by it (Rafael Wysocki) - Make the hibernation core code complain about memory map mismatches during resume to help diagnostics (Xueqin Luo) - Fix mistake in a kerneldoc comment in the hibernation code (xiongxin) - Reverse the order of performance and enabling operations in the generic power domains code (Abel Vesa) - Power off[on] domains in hibernate .freeze[thaw]_noirq hook of in the generic power domains code (Abel Vesa) - Consolidate genpd_restore_noirq() and genpd_resume_noirq() (Shawn Guo) - Pass generic PM noirq hooks to genpd_finish_suspend() (Shawn Guo) - Drop generic power domain status manipulation during hibernate restore (Shawn Guo) - Fix compiler warnings with make W=1 in the idle_inject power capping driver (Srinivas Pandruvada) - Use kstrtobool() instead of strtobool() in the power capping sysfs interface (Christophe JAILLET) - Add SCMI Powercap based power capping driver (Cristian Marussi) - Add Emerald Rapids support to the intel-uncore-freq driver (Artem Bityutskiy) - Repair slips in kernel-doc comments in the generic notifier code (Lukas Bulwahn) - Fix several DT issues in the OPP library reorganize code around opp-microvolt-<named> DT property (Viresh Kumar) - Allow any of opp-microvolt, opp-microamp, or opp-microwatt properties to be present without the others present (James Calligeros) - Fix clock-latency-ns property in DT example (Serge Semin) - Add a private governor_data for devfreq governors (Kant Fan) - Reorganize devfreq code to use device_match_of_node() and devm_platform_get_and_ioremap_resource() instead of open coding them (ye xingchen, Minghao Chi) - Make cpupower choose base_cpu to display default cpupower details instead of picking CPU 0 (Saket Kumar Bhaskar) - Add Georgian translation to cpupower documentation (Zurab Kargareteli) - Introduce powercap intel-rapl library, powercap-info command, and RAPL monitor into cpupower (Thomas Renninger)" * tag 'pm-6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (64 commits) PM: runtime: Adjust white space in the core code cpufreq: Remove CVS version control contents from documentation cpufreq: stats: Convert to use sysfs_emit_at() API cpufreq: ACPI: Only set boost MSRs on supported CPUs PM: sleep: Refine error message in try_to_freeze_tasks() PM: sleep: Avoid using pr_cont() in the tasks freezing code PM: runtime: Relocate rpm_callback() right after __rpm_callback() PM: runtime: Do not call __rpm_callback() from rpm_idle() PM / devfreq: event: use devm_platform_get_and_ioremap_resource() PM / devfreq: event: Use device_match_of_node() PM / devfreq: Use device_match_of_node() powercap: idle_inject: Fix warnings with make W=1 PM: hibernate: Complain about memory map mismatches during resume dt-bindings: cpufreq: cpufreq-qcom-hw: Add QDU1000/QRU1000 cpufreq cpufreq: tegra186: Use flexible array to simplify memory allocation cpupower: rapl monitor - shows the used power consumption in uj for each rapl domain cpupower: Introduce powercap intel-rapl library and powercap-info command cpupower: Add Georgian translation cpufreq: intel_pstate: Add Sapphire Rapids support in no-HWP mode cpufreq: amd_freq_sensitivity: Add missing pci_dev_put() ...
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