index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
arch
/
arm64
/
include
/
asm
/
cpu.h
Age
Commit message (
Expand
)
Author
Files
Lines
2023-06-06
arm64: cpufeature: add system register ID_AA64MMFR3
Joey Gouly
1
-0
/
+1
2022-06-23
arm64/sme: Expose SMIDR through sysfs
Mark Brown
1
-0
/
+1
2022-04-22
arm64/sme: Identify supported SME vector lengths at boot
Mark Brown
1
-0
/
+3
2022-04-22
arm64/sme: Basic enumeration support
Mark Brown
1
-0
/
+1
2021-12-13
arm64: add ID_AA64ISAR2_EL1 sys register
Joey Gouly
1
-0
/
+1
2021-06-11
arm64: cpuinfo: Split AArch32 registers out into a separate struct
Will Deacon
1
-21
/
+25
2021-05-27
arm64: Check if GMID_EL1.BS is the same on all CPUs
Catalin Marinas
1
-0
/
+1
2021-05-27
arm64: Change the cpuinfo_arm64 member type for some sysregs to u64
Catalin Marinas
1
-5
/
+5
2020-05-21
arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context
Anshuman Khandual
1
-0
/
+1
2020-05-21
arm64/cpufeature: Introduce ID_MMFR5 CPU register
Anshuman Khandual
1
-0
/
+1
2020-05-21
arm64/cpufeature: Introduce ID_DFR1 CPU register
Anshuman Khandual
1
-0
/
+1
2020-05-21
arm64/cpufeature: Introduce ID_PFR2 CPU register
Anshuman Khandual
1
-0
/
+1
2020-01-15
arm64: Introduce ID_ISAR6 CPU register
Anshuman Khandual
1
-0
/
+1
2019-06-19
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234
Thomas Gleixner
1
-12
/
+1
2017-11-03
arm64/sve: Probe SVE capabilities and usable vector lengths
Dave Martin
1
-0
/
+4
2016-07-12
arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs
Steve Capper
1
-0
/
+2
2016-02-18
arm64: add ARMv8.2 id_aa64mmfr2 boiler plate
James Morse
1
-0
/
+1
2015-10-21
arm64: Consolidate CPU Sanity check to CPU Feature infrastructure
Suzuki K. Poulose
1
-1
/
+2
2015-10-21
arm64: Keep track of CPU feature registers
Suzuki K. Poulose
1
-0
/
+1
2015-10-21
arm64: Move mixed endian support detection
Suzuki K. Poulose
1
-0
/
+2
2015-01-07
arm64: sanity checks: add missing AArch32 registers
Mark Rutland
1
-0
/
+5
2014-11-25
arm64: sanity checks: add ID_AA64DFR{0,1}_EL1
Mark Rutland
1
-0
/
+2
2014-07-18
arm64: cpuinfo: record cpu system register values
Mark Rutland
1
-0
/
+59