| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-01-18 | Merge patch series "riscv: Add fine-tuned checksum functions" | Palmer Dabbelt | 1 | -0/+2 |
| 2024-01-18 | riscv: Add static key for misaligned accesses | Charlie Jenkins | 1 | -0/+2 |
| 2023-12-13 | riscv: add ISA extension parsing for scalar crypto | Evan Green | 1 | -1/+3 |
| 2023-11-09 | riscv: Rearrange hwcap.h and cpufeature.h | Xiao Wang | 1 | -0/+83 |
| 2023-11-08 | RISC-V: Probe misaligned access speed in parallel | Evan Green | 1 | -1/+0 |
| 2023-11-05 | Merge patch series "Add support to handle misaligned accesses in S-mode" | Palmer Dabbelt | 1 | -0/+18 |
| 2023-11-01 | riscv: report misaligned accesses emulation to hwprobe | Clément Léger | 1 | -0/+18 |
| 2023-09-21 | RISC-V: Enable cbo.zero in usermode | Andrew Jones | 1 | -0/+1 |
| 2023-09-01 | RISC-V: Probe for unaligned access speed | Evan Green | 1 | -0/+2 |
| 2023-06-19 | RISC-V: Track ISA extensions per hart | Evan Green | 1 | -0/+10 |
| 2023-04-19 | RISC-V: hwprobe: Support probing of misaligned access performance | Evan Green | 1 | -0/+2 |
| 2023-04-19 | RISC-V: Move struct riscv_cpuinfo to new header | Evan Green | 1 | -0/+21 |
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index : starfive-tech/linux.git | |
| StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror) | Andrey V.Kosteltsev |
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