Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-06-10 | cxl/acpi: Introduce the root of a cxl_port topology | Dan Williams | 1 | -0/+31 |
2021-06-06 | cxl/pci: Add HDM decoder capabilities | Ben Widawsky | 1 | -6/+59 |
2021-06-06 | cxl/pci: Map registers based on capabilities | Ira Weiny | 1 | -5/+28 |
2021-05-15 | cxl/core: Refactor CXL register lookup for bridge reuse | Dan Williams | 1 | -0/+3 |
2021-05-15 | cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices | Dan Williams | 1 | -0/+32 |
2021-05-15 | cxl/mem: Move some definitions to mem.h | Dan Williams | 1 | -57/+0 |
2021-02-17 | cxl/mem: Enable commands via CEL | Ben Widawsky | 1 | -0/+2 |
2021-02-17 | cxl/mem: Register CXL memX devices | Dan Williams | 1 | -0/+3 |
2021-02-17 | cxl/mem: Find device capabilities | Ben Widawsky | 1 | -0/+90 |