index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
drivers
/
fpga
/
zynq-fpga.c
Age
Commit message (
Expand
)
Author
Files
Lines
2023-12-21
fpga: zynq-fpga: Convert to platform remove callback returning void
Uwe Kleine-König
1
-4
/
+2
2023-07-10
fpga: zynq-fpga: Convert to devm_platform_ioremap_resource()
Yangtao Li
1
-3
/
+1
2023-06-06
fpga: zynq-fpga: Ensure proper xCAP interface switch
Alfonso Rodriguez
1
-4
/
+4
2022-10-25
fpga: zynq: Switch to use dev_err_probe() helper
Yang Yingliang
1
-5
/
+3
2021-11-29
fpga: mgr: Use standard dev_release for class driver
Russ Weight
1
-10
/
+6
2021-07-22
fpga: fix spelling mistakes
Tom Rix
1
-3
/
+3
2020-03-31
fpga: zynq: Remove clk_get error message for probe defer
Shubhrajyoti Datta
1
-1
/
+2
2019-10-05
fpga: Remove dev_err() usage after platform_get_irq()
Stephen Boyd
1
-3
/
+1
2019-06-05
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285
Thomas Gleixner
1
-9
/
+1
2018-11-11
zynq-fpga: Only route PR via PCAP when required
Mike Looijmans
1
-0
/
+4
2018-10-16
fpga: mgr: add devm_fpga_mgr_create
Alan Tull
1
-3
/
+2
2018-05-25
fpga: manager: change api, don't use drvdata
Alan Tull
1
-3
/
+11
2017-03-17
fpga: zynq: Add support for encrypted bitstreams
Moritz Fischer
1
-3
/
+25
2017-02-10
fpga zynq: Use the scatterlist interface
Jason Gunthorpe
1
-39
/
+135
2017-02-10
fpga zynq: Check the bitstream for validity
Jason Gunthorpe
1
-0
/
+21
2017-02-10
fpga zynq: Check for errors after completing DMA
Jason Gunthorpe
1
-22
/
+32
2016-11-30
fpga zynq: Fix incorrect ISR state on bootup
Jason Gunthorpe
1
-7
/
+10
2016-11-30
fpga zynq: Remove priv->dev
Jason Gunthorpe
1
-11
/
+8
2016-11-30
fpga zynq: Add missing \n to messages
Jason Gunthorpe
1
-11
/
+11
2016-11-10
fpga-mgr: add fpga image information struct
Alan Tull
1
-4
/
+6
2015-10-24
fpga: zynq-fpga: Fix issue with drvdata being overwritten.
Moritz Fischer
1
-3
/
+4
2015-10-24
fpga: zynq-fpga: Change fw format to handle bin instead of bit.
Moritz Fischer
1
-22
/
+2
2015-10-24
fpga: zynq-fpga: Fix unbalanced clock handling
Moritz Fischer
1
-2
/
+2
2015-10-18
fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000
Moritz Fischer
1
-0
/
+533