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path: root/drivers/gpu/drm/xe/regs
AgeCommit message (Expand)AuthorFilesLines
2023-12-21drm/xe: Separate number of registers from MI_LRI opcodeMatt Roper1-1/+3
2023-12-21drm/xe: Make MI_FLUSH_DW immediate size more explicitMatt Roper1-1/+4
2023-12-21drm/xe/gsc: add HECI2 register offsetsVitaly Lubart1-0/+4
2023-12-21drm/xe: add 28-bit address support in struct xe_regKoby Elbaz1-1/+15
2023-12-21drm/xe: add gt tuning for indirect stateMatt Atwood1-0/+1
2023-12-21drm/xe: Remove devcoredump readout of IPEIRJosé Roberto de Souza1-2/+0
2023-12-21drm/xe: Fix devcoredump readout of IPEHRJosé Roberto de Souza1-1/+0
2023-12-21drm/xe/hwmon: Expose hwmon energy attributeBadal Nilawar2-0/+5
2023-12-21drm/xe/hwmon: Expose input voltage attributeBadal Nilawar1-0/+3
2023-12-21drm/xe/hwmon: Expose power attributesBadal Nilawar2-0/+37
2023-12-21drm/xe/xe2: Update MOCS fields in blitter instructionsHaridhar Kalvala1-0/+4
2023-12-21drm/xe/xe2: Set tile y type in XY_FAST_COPY_BLT to Tile4Haridhar Kalvala1-0/+2
2023-12-21drm/xe: Rename MEM_SET instructionHaridhar Kalvala1-3/+3
2023-12-21drm/xe: Adjust mocs field mask definitionsHaridhar Kalvala1-2/+2
2023-12-21drm/xe/xe2: Extend reserved stolen sizesLucas De Marchi1-1/+1
2023-12-21drm/xe: Add Wa_18028616096Shekhar Chauhan1-0/+1
2023-12-21drm/xe/wa: Apply tile workarounds at probe/resumeMatt Roper1-0/+3
2023-12-21drm/xe/pmu: Enable PMU interfaceAravind Iddamsetty1-0/+5
2023-12-21drm/xe/pvc: Force even num engines to use 64BNiranjana Vishwanathapura1-0/+1
2023-12-21drm/xe/pvc: Blacklist BCS_SWCTRL registerNiranjana Vishwanathapura1-0/+2
2023-12-21drm/xe/xe2: Program GuC's MOCS on Xe2 and beyondMatt Roper1-1/+1
2023-12-21drm/xe/xe2: Handle fused-off CCS enginesMatt Roper1-0/+1
2023-12-21drm/xe/xe2: Add MCR register steering for primary GTMatt Roper1-0/+1
2023-12-21drm/xe/xe2: Add GT topology readoutMatt Roper1-0/+3
2023-12-21drm/xe: enable idle msg and set hysteresis for GSCCSDaniele Ceraolo Spurio1-0/+4
2023-12-21drm/xe: GSC forcewake supportDaniele Ceraolo Spurio1-0/+2
2023-12-21drm/xe: add GSCCS irq supportDaniele Ceraolo Spurio1-0/+2
2023-12-21drm/xe: base definitions for the GSCCSDaniele Ceraolo Spurio2-0/+2
2023-12-21drm/xe/dg2: Remove Wa_15010599737Shekhar Chauhan1-3/+0
2023-12-21drm/xe: Add Wa_14015150844 for DG2 and Xe_LPGMatt Roper1-0/+1
2023-12-21drm/xe: Sort xe_regs.hLucas De Marchi1-30/+33
2023-12-21drm/xe: Carve out top of DSM as reservedLucas De Marchi1-0/+3
2023-12-21drm/xe/mtl: Add support to get C6 residency/status of MTLBadal Nilawar1-2/+9
2023-12-21drm/xe/mtl: Add some initial MTL workaroundsMatt Roper1-0/+8
2023-12-20drm/xe: Emit a render cache flush after each rcs/ccs batchThomas Hellström1-0/+3
2023-12-20drm/xe: Invalidate TLB also on bind if in scratch page modeThomas Hellström1-0/+1
2023-12-20drm/xe: Don't hardcode GuC's MOCS index in register headerMatt Roper1-4/+1
2023-12-20drm/xe: Reformat xe_guc_regs.hMatt Roper1-93/+93
2023-12-20drm/xe: Reinstate media GT supportMatt Roper1-0/+8
2023-12-20drm/xe: Rework size helper to be a little more correctMichael J. Ruhl1-1/+1
2023-12-20drm/xe: Add stepping support for GMD_ID platformsMatt Roper1-1/+1
2023-12-20drm/xe: Move Media GuC register definition to regs/Michal Wajdeczko1-0/+2
2023-12-20drm/xe: Rename reg field to addrLucas De Marchi1-3/+3
2023-12-20drm/xe/guc: Handle RCU_MODE as masked from definitionLucas De Marchi1-1/+1
2023-12-20drm/xe: Set default MOCS value for copy cs instructionsJosé Roberto de Souza1-0/+6
2023-12-20drm/xe: Set default MOCS value for cs instructionsJosé Roberto de Souza1-0/+12
2023-12-20drm/xe: Annotate masked registers used by RTPLucas De Marchi2-25/+25
2023-12-20drm/xe: Use XE_REG/XE_REG_MCRLucas De Marchi5-209/+201
2023-12-20drm/xe: Introduce xe_reg/xe_reg_mcrLucas De Marchi1-0/+95
2023-12-20drm/xe: Use REG_FIELD/REG_BIT for all regs/*.hLucas De Marchi3-52/+42
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