path: root/arch/riscv/boot/dts/starfive/jh7100.dtsi

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2021 StarFive Technology Co., Ltd.
 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
 */

/dts-v1/;
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/clock/starfive-jh7100-audio.h>
#include <dt-bindings/reset/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100-audio.h>

/ {
	compatible = "starfive,jh7100";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		U74_0: cpu@0 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			starfive,itim = <&itim0>;
			tlb-split;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <1>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <32>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <32>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			starfive,itim = <&itim1>;
			tlb-split;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&U74_0>;
				};

				core1 {
					cpu = <&U74_1>;
				};
			};
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <15000>;

			thermal-sensors = <&sfctemp>;

			trips {
				cpu-alert0 {
					/* milliCelsius */
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu-crit {
					/* milliCelsius */
					temperature = <90000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	osc_sys: osc-sys {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "osc_sys";
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	osc_aud: osc-aud {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "osc_aud";
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	gmac_rmii_ref: gmac-rmii-ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "gmac_rmii_ref";
		/* Should be overridden by the board when needed */
		clock-frequency = <0>;
	};

	gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-output-names = "gmac_gr_mii_rxclk";
		/* Should be overridden by the board when needed */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		dma-noncoherent;
		ranges;

		dtim: dtim@1000000 {
			compatible = "starfive,dtim0";
			reg = <0x0 0x1000000 0x0 0x2000>;
			reg-names = "mem";
		};

		itim0: itim@1808000 {
			compatible = "starfive,itim0";
			reg = <0x0 0x1808000 0x0 0x8000>;
			reg-names = "mem";
		};

		itim1: itim@1820000 {
			compatible = "starfive,itim0";
			reg = <0x0 0x1820000 0x0 0x8000>;
			reg-names = "mem";
		};

		clint: clint@2000000 {
			compatible = "starfive,jh7100-clint", "sifive,clint0";
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>;
		};

		ccache: cache-controller@2010000 {
			compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
			reg = <0x0 0x2010000 0x0 0x1000>;
			interrupts = <128>, <130>, <131>, <129>;
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <2048>;
			cache-size = <2097152>;
			cache-unified;
		};

		plic: interrupt-controller@c000000 {
			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
			reg = <0x0 0xc000000 0x0 0x4000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
			riscv,ndev = <133>;
		};

		sdio0: mmc@10000000 {
			compatible = "snps,dw-mshc";
			reg = <0x0 0x10000000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
				 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
			clock-names = "biu", "ciu";
			interrupts = <4>;
			data-addr = <0>;
			fifo-depth = <32>;
			fifo-watermark-aligned;
			status = "disabled";
		};

		sdio1: mmc@10010000 {
			compatible = "snps,dw-mshc";
			reg = <0x0 0x10010000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
				 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
			clock-names = "biu", "ciu";
			interrupts = <5>;
			data-addr = <0>;
			fifo-depth = <32>;
			fifo-watermark-aligned;
			status = "disabled";
		};

		gmac: ethernet@10020000 {
			compatible = "starfive,jh7100-dwmac", "snps,dwmac";
			reg = <0x0 0x10020000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
				 <&clkgen JH7100_CLK_GMAC_AHB>,
				 <&clkgen JH7100_CLK_GMAC_PTP_REF>,
				 <&clkgen JH7100_CLK_GMAC_TX_INV>,
				 <&clkgen JH7100_CLK_GMAC_GTX>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
			resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
			reset-names = "ahb";
			interrupts = <6>, <7>;
			interrupt-names = "macirq", "eth_wake_irq";
			max-frame-size = <9000>;
			snps,multicast-filter-bins = <32>;
			snps,perfect-filter-entries = <128>;
			starfive,syscon = <&sysmain 0x70 0>;
			rx-fifo-depth = <32768>;
			tx-fifo-depth = <16384>;
			snps,axi-config = <&stmmac_axi_setup>;
			snps,fixed-burst;
			snps,force_thresh_dma_mode;
			status = "disabled";

			stmmac_axi_setup: stmmac-axi-config {
				snps,wr_osr_lmt = <16>;
				snps,rd_osr_lmt = <16>;
				snps,blen = <256 128 64 32 0 0 0>;
			};
		};

		dma2p: dma-controller@100b0000 {
			compatible = "starfive,jh7100-axi-dma";
			reg = <0x0 0x100b0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
				 <&clkgen JH7100_CLK_SGDMA2P_AHB>;
			clock-names = "core-clk", "cfgr-clk";
			resets = <&rstgen JH7100_RSTN_SGDMA2P_AXI>,
				 <&rstgen JH7100_RSTN_SGDMA2P_AHB>;
			reset-names = "axi", "ahb";
			interrupts = <2>;
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,block-size = <4096 4096 4096 4096>;
			snps,priority = <0 1 2 3>;
			snps,axi-max-burst-len = <128>;
			dma-coherent;
		};

		crypto: crypto@100d0000 {
			compatible = "starfive,vic-sec";
			reg = <0x0 0x100d0000 0x0 0x20000>,
			      <0x0 0x11800234 0x0 0xc>;
			reg-names = "secmem", "secclk";
			clocks = <&clkgen JH7100_CLK_SEC_AHB>;
			interrupts = <31>;
		};

		i2sadc0: i2sadc0@10400000 {
			compatible = "snps,designware-i2sadc0";
			reg = <0x0 0x10400000 0x0 0x1000>;
			clocks = <&clkgen JH7100_CLK_APB1_BUS>;
			clock-names = "i2sclk";
			interrupt-parent = <&plic>;
			#sound-dai-cells = <0>;
			dmas = <&dma2p 28>;
			dma-names = "rx";
		};

		i2svad: i2svad@10420000 {
			compatible = "starfive,sf-i2svad";
			reg = <0x0 0x10420000 0x0 0x1000> ;
			clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
			clock-names = "i2svad_apb";
			resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
				 <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
			reset-names = "apb_i2svad", "i2svad_srst";
			interrupts = <60>, <61>;
			interrupt-names = "spintr", "slintr";
			#sound-dai-cells = <0>;
		};

		pwmdac: pwmdac@10440000 {
			compatible = "starfive,pwmdac";
			reg = <0x0 0x10440000 0x0 0x1000>;
			clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
				 <&clkgen JH7100_CLK_AUDIO_SRC>,
				 <&clkgen JH7100_CLK_AUDIO_12288>,
				 <&audclk JH7100_AUDCLK_DMA1P_AHB>,
				 <&audclk JH7100_AUDCLK_PWMDAC_APB>,
				 <&audclk JH7100_AUDCLK_DAC_MCLK>;
			clock-names = "audio_root",
				      "audio_src",
				      "audio_12288",
				      "dma1p_ahb",
				      "pwmdac_apb",
				      "dac_mclk";
			resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
				 <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
				 <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
			reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
			dmas = <&dma2p 23>;
			dma-names = "tx";
			#sound-dai-cells = <0>;
		};

		i2sdac0: i2sdac0@10450000 {
			compatible = "snps,designware-i2sdac0";
			reg = <0x0 0x10450000 0x0 0x1000>;
			clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
				 <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
				 <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
				 <&audclk JH7100_AUDCLK_I2SDAC_APB>;
			clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
			resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
				 <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
			reset-names = "apb_i2sdac", "i2sdac_srst";
			#sound-dai-cells = <0>;
			dmas = <&dma2p 30>;
			dma-names = "tx";
		};

		i2sdac1: i2sdac1@10460000 {
			compatible = "snps,designware-i2sdac1";
			reg = <0x0 0x10460000 0x0 0x1000>;
			clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
				 <&audclk JH7100_AUDCLK_I2S1_BCLK>,
				 <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
				 <&audclk JH7100_AUDCLK_I2S1_APB>;
			clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
			resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
				 <&audrst JH7100_AUDRSTN_I2S1_SRST>;
			#sound-dai-cells = <0>;
			dmas = <&dma2p 31>;
			dma-names = "tx";
		};

		i2sdac16k: i2sdac16k@10470000 {
			compatible = "snps,designware-i2sdac16k";
			reg = <0x0 0x10470000 0x0 0x1000>;
			clocks = <&clkgen JH7100_CLK_APB1_BUS>;
			clock-names = "i2sclk";
			#sound-dai-cells = <0>;
			dmas = <&dma2p 29>;
			dma-names = "tx";
		};

		audclk: clock-controller@10480000 {
			compatible = "starfive,jh7100-audclk";
			reg = <0x0 0x10480000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
				 <&clkgen JH7100_CLK_AUDIO_12288>,
				 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
			clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
			#clock-cells = <1>;
		};

		audrst: reset-controller@10490000 {
			compatible = "starfive,jh7100-audrst";
			reg = <0x0 0x10490000 0x0 0x10000>;
			#reset-cells = <1>;
		};

		spdif_transmitter: spdif-transmitter {
			compatible = "linux,spdif-dit";
			#sound-dai-cells = <0>;
		};

		spdif_receiver: spdif-receiver {
			compatible = "linux,spdif-dir";
			#sound-dai-cells = <0>;
		};

		pwmdac_codec: pwmdac-transmitter {
			compatible = "linux,pwmdac-dit";
			#sound-dai-cells = <0>;
		};

		dmic_codec: dmic {
			compatible = "dmic-codec";
			#sound-dai-cells = <0>;
		};

		sound: snd-card {
			compatible = "simple-audio-card";
			simple-audio-card,name = "Starfive-Multi-Sound-Card";
			#address-cells = <1>;
			#size-cells = <0>;

			/* pwmdac */
			simple-audio-card,dai-link@0 {
				reg = <0>;
				status = "okay";
				format = "left_j";
				bitclock-master = <&sndcpu0>;
				frame-master = <&sndcpu0>;

				sndcpu0: cpu {
					sound-dai = <&pwmdac>;
				};

				codec {
					sound-dai = <&pwmdac_codec>;
				};
			};
		};

		sysaudio: syscon@104a0000 {
			compatible = "starfive,jh7100-sysaudio", "syscon";
			reg = <0x0 0x104a0000 0x0 0x10000>;
		};

		usb3: usb@104c0000 {
			compatible = "starfive,jh7100-usb";
			ranges = <0x0 0x0 0x104c0000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&audclk JH7100_AUDCLK_USB_LPM>,
			         <&audclk JH7100_AUDCLK_USB_STB>,
			         <&clkgen JH7100_CLK_USB_AXI>,
			         <&clkgen JH7100_CLK_USBNOC_AXI>;
			clock-names = "lpm", "stb", "axi", "nocaxi";
			resets = <&rstgen JH7100_RSTN_USB_AXI>,
			         <&rstgen JH7100_RSTN_USBNOC_AXI>;
			reset-names = "axi", "nocaxi";
			starfive,syscon = <&sysaudio>;
			status = "disabled";

			usb_cdns3: usb@0 {
				compatible = "cdns,usb3";
				reg = <0x00000 0x10000>,
				      <0x10000 0x10000>,
				      <0x20000 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <44>, <52>, <43>;
				interrupt-names = "host", "peripheral", "otg";
			};
		};

		dma1p: dma-controller@10500000 {
			compatible = "starfive,jh7100-axi-dma";
			reg = <0x0 0x10500000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
				 <&clkgen JH7100_CLK_SGDMA1P_BUS>;
			clock-names = "core-clk", "cfgr-clk";
			resets = <&rstgen JH7100_RSTN_DMA1P_AXI>,
				 <&rstgen JH7100_RSTN_SGDMA1P_AXI>;
			reset-names = "axi", "ahb";
			interrupts = <1>;
			#dma-cells = <1>;
			dma-channels = <16>;
			snps,dma-masters = <1>;
			snps,data-width = <3>;
			snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
			snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
			snps,axi-max-burst-len = <64>;
		};

		clkgen: clock-controller@11800000 {
			compatible = "starfive,jh7100-clkgen";
			reg = <0x0 0x11800000 0x0 0x10000>;
			clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
			clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
			#clock-cells = <1>;
		};

		otp: otp@11810000 {
			compatible = "starfive,fu740-otp";
			reg = <0x0 0x11810000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_OTP_APB>;
			fuse-count = <0x200>;
		};

		rstgen: reset-controller@11840000 {
			compatible = "starfive,jh7100-reset";
			reg = <0x0 0x11840000 0x0 0x10000>;
			#reset-cells = <1>;
		};

		sysmain: syscon@11850000 {
			compatible = "starfive,jh7100-sysmain", "syscon";
			reg = <0x0 0x11850000 0x0 0x10000>;
		};

		qspi: spi@11860000 {
			compatible = "cdns,qspi-nor";
			reg = <0x0 0x11860000 0x0 0x10000>,
			      <0x0 0x20000000 0x0 0x20000000>;
			clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
			interrupts = <3>;
			#address-cells = <1>;
			#size-cells = <0>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			spi-max-frequency = <250000000>;
			status = "disabled";
		};

		uart0: serial@11870000 {
			compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
			reg = <0x0 0x11870000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART0_CORE>,
				 <&clkgen JH7100_CLK_UART0_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART0_APB>;
			interrupts = <92>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart1: serial@11880000 {
			compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
			reg = <0x0 0x11880000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART1_CORE>,
				 <&clkgen JH7100_CLK_UART1_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART1_APB>;
			interrupts = <93>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		spi0: spi@11890000 {
			compatible = "snps,dw-apb-ssi";
			reg = <0x0 0x11890000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
				 <&clkgen JH7100_CLK_SPI0_APB>;
			clock-names = "ssi_clk", "pclk";
			resets = <&rstgen JH7100_RSTN_SPI0_APB>;
			reset-names = "spi";
			interrupts = <94>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@118a0000 {
			compatible = "snps,dw-apb-ssi";
			reg = <0x0 0x118a0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
				 <&clkgen JH7100_CLK_SPI1_APB>;
			clock-names = "ssi_clk", "pclk";
			resets = <&rstgen JH7100_RSTN_SPI1_APB>;
			reset-names = "spi";
			interrupts = <95>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@118b0000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118b0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
				 <&clkgen JH7100_CLK_I2C0_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C0_APB>;
			interrupts = <96>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@118c0000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x118c0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
				 <&clkgen JH7100_CLK_I2C1_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C1_APB>;
			interrupts = <97>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		trng: trng@118d0000 {
			compatible = "starfive,vic-rng";
			reg = <0x0 0x118d0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_TRNG_APB>;
			interrupts = <98>;
		};

		vpu_enc: vpu_enc@118e0000 {
			compatible = "cm,cm521-vpu";
			reg = <0x0 0x118e0000 0x0 0x4000>;
			reg-names = "control";
			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
			clock-names = "vcodec";
			interrupts = <26>;
		};

		vpu_dec: vpu_dec@118f0000 {
			compatible = "c&m,cm511-vpu";
			reg = <0 0x118f0000 0 0x10000>;
			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
			clock-names = "vcodec";
			interrupts = <23>;
			//memory-region = <&vpu_reserved>;
		};

		jpu: coadj12@11900000 {
			compatible = "cm,codaj12-jpu-1";
			reg = <0x0 0x11900000 0x0 0x300>;
			reg-names = "control";
			clocks = <&clkgen JH7100_CLK_JPEG_APB>;
			clock-names = "jpege";
			interrupts = <24>;
			memory-region = <&jpu_reserved>;
		};

		gpio: pinctrl@11910000 {
			compatible = "starfive,jh7100-pinctrl";
			reg = <0x0 0x11910000 0x0 0x10000>,
			      <0x0 0x11858000 0x0 0x1000>;
			reg-names = "gpio", "padctl";
			clocks = <&clkgen JH7100_CLK_GPIO_APB>;
			resets = <&rstgen JH7100_RSTN_GPIO_APB>;
			interrupts = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		nvdla@11940000 {
			compatible = "nvidia,nvdla_os_initial";
			interrupts = <22>;
			memory-region = <&nvdla_reserved>;
			reg = <0x0 0x11940000 0x0 0x40000>;
			status = "okay";
		};

		display: display-subsystem {
			compatible = "starfive,display-subsystem";
			dma-coherent;
			status = "disabled";
		};

		encoder: display-encoder {
			compatible = "starfive,display-encoder";
			status = "disabled";
		};

		crtc: crtc@12000000 {
			compatible = "starfive,jh7100-crtc";
			reg = <0x0 0x12000000 0x0 0x10000>,
			      <0x0 0x12040000 0x0 0x10000>,
			      <0x0 0x12080000 0x0 0x10000>,
			      <0x0 0x120c0000 0x0 0x10000>,
			      <0x0 0x12240000 0x0 0x10000>,
			      <0x0 0x12250000 0x0 0x10000>,
			      <0x0 0x12260000 0x0 0x10000>;
			reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
			clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
			clock-names = "disp_axi", "vout_src";
			resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
			reset-names = "disp_axi", "vout_src";
			interrupts = <101>, <103>;
			interrupt-names = "lcdc_irq", "vpp1_irq";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			pp1 {
				pp-id = <1>;
				fifo-out;
				//sys-bus-out;
				src-format = <11>; //<COLOR_RGB565>;
				src-width = <1920>;
				src-height = <1080>;
				dst-format = <7>; //<COLOR_RGB888_ARGB>;
				dst-width = <1920>;
				dst-height = <1080>;
			};
		};

		spi2: spi@12410000 {
			compatible = "snps,dw-apb-ssi";
			reg = <0x0 0x12410000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
				 <&clkgen JH7100_CLK_SPI2_APB>;
			clock-names = "ssi_clk", "pclk";
			resets = <&rstgen JH7100_RSTN_SPI2_APB>;
			reset-names = "spi";
			interrupts = <70>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@12420000 {
			compatible = "snps,dw-apb-ssi";
			reg = <0x0 0x12420000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
				 <&clkgen JH7100_CLK_SPI3_APB>;
			clock-names = "ssi_clk", "pclk";
			resets = <&rstgen JH7100_RSTN_SPI3_APB>;
			reset-names = "spi";
			interrupts = <71>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		uart2: serial@12430000 {
			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
			reg = <0x0 0x12430000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART2_CORE>,
				 <&clkgen JH7100_CLK_UART2_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART2_APB>;
			interrupts = <72>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart3: serial@12440000 {
			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
			reg = <0x0 0x12440000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_UART3_CORE>,
				 <&clkgen JH7100_CLK_UART3_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&rstgen JH7100_RSTN_UART3_APB>;
			interrupts = <73>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		i2c2: i2c@12450000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12450000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
				 <&clkgen JH7100_CLK_I2C2_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C2_APB>;
			interrupts = <74>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@12460000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12460000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
				 <&clkgen JH7100_CLK_I2C3_APB>;
			clock-names = "ref", "pclk";
			resets = <&rstgen JH7100_RSTN_I2C3_APB>;
			interrupts = <75>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		watchdog@12480000 {
			compatible = "starfive,jh7100-wdt";
			reg = <0x0 0x12480000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
				 <&clkgen JH7100_CLK_WDT_CORE>;
			clock-names = "apb", "core";
			resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
				 <&rstgen JH7100_RSTN_WDT>;
		};

		pwm: pwm@12490000 {
			compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
			reg = <0x0 0x12490000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_PWM_APB>;
			resets = <&rstgen JH7100_RSTN_PWM_APB>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		sfctemp: temperature-sensor@124a0000 {
			compatible = "starfive,jh7100-temp";
			reg = <0x0 0x124a0000 0x0 0x10000>;
			clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
				 <&clkgen JH7100_CLK_TEMP_APB>;
			clock-names = "sense", "bus";
			resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
				 <&rstgen JH7100_RSTN_TEMP_APB>;
			reset-names = "sense", "bus";
			#thermal-sensor-cells = <0>;
		};

		xrp@f0000000 {
			compatible = "cdns,xrp";
			reg = <0x0  0xf0000000 0x0 0x01ffffff>,
			      <0x10 0x72000000 0x0 0x00001000>,
			      <0x10 0x72001000 0x0 0x00fff000>,
			      <0x0  0x124b0000 0x0 0x00010000>;
			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
			interrupts = <27>, <28>;
			firmware-name = "vp6_elf";
			dsp-irq = <19 20>;
			dsp-irq-src = <0x20 0x21>;
			intc-irq-mode = <1>;
			intc-irq = <0 1>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x40000000 0x0  0x40000000 0x01000000>,
				 <0xb0000000 0x10 0x70000000 0x3000000>;
			dsp@0 {
			};
		};
	};
};