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starfive-tech/u-boot.git
Fedora_JH7100_2021.04
Fedora_JH7100_2021.07
Fedora_JH7100_upstream
Fedora_JH7100_upstream_devel
JH7100_Multimedia_V0.1.0
JH7100_VisionFive_OH_dev
JH7100_VisionFive_devel
JH7100_starlight_multimedia
JH7100_upstream
JH7100_upstream_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_devel-v3.9.3
dubhe_fpga_dev_v2023.10
master
rtthread_AMP
visionfive_devel
StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
arm
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mach-sunxi
/
dram_sunxi_dw.c
Age
Commit message (
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Author
Files
Lines
2020-05-19
common: Drop log.h from common header
Simon Glass
1
-0
/
+1
2020-05-19
common: Drop init.h from common header
Simon Glass
1
-0
/
+1
2018-05-07
SPDX: Convert all of our single license tags to Linux Kernel style
Tom Rini
1
-2
/
+1
2017-06-08
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
Icenowy Zheng
1
-0
/
+2
2017-06-08
sunxi: add support for V3s DRAM controller
Icenowy Zheng
1
-0
/
+3
2017-06-08
sunxi: add support for the DDR2 in V3s SoC
Icenowy Zheng
1
-0
/
+2
2017-06-08
sunxi: enable dual rank detection in DesignWare-like DRAM code
Icenowy Zheng
1
-1
/
+3
2017-06-08
sunxi: Add selective DRAM type and timing
Icenowy Zheng
1
-113
/
+6
2017-06-08
sunxi: add bank detection code to H3 DRAM initialization code
Icenowy Zheng
1
-4
/
+15
2017-06-08
sunxi: add option for 16-bit DW DRAM controller
Icenowy Zheng
1
-4
/
+29
2017-06-08
sunxi: Rename bus-width related macros in H3 DRAM code
Icenowy Zheng
1
-5
/
+6
2017-06-08
sunxi: makes an invisible option for H3-like DRAM controllers
Icenowy Zheng
1
-0
/
+829