starfive-tech/u-boot.git - StarFive Tech U-Boot for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2023-02-17	riscv: Rename Andes cpu and board names	Leo Yu-Chi Liang	1	-130/+0
2023-02-17	riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL	Yu Chien Peter Lin	1	-30/+68
2023-02-17	riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"	Leo Yu-Chi Liang	1	-82/+2
2020-05-19	common: Drop net.h from common header	Simon Glass	1	-0/+1
2020-04-23	riscv: ax25: cache: Remove SPL_RISCV_MMODE config check	Pragnesh Patel	1	-8/+8
2019-12-10	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	Rick Chen	1	-14/+46
2019-12-03	common: Move some cache and MMU functions out of common.h	Simon Glass	1	-0/+1
2019-09-03	riscv: cache: use CCTL to flush d-cache	Rick Chen	1	-9/+13
2019-09-03	riscv: cache: Flush L2 cache before jump to linux	Rick Chen	1	-0/+17
2019-05-18	CONFIG_SPL_SYS_[DI]CACHE_OFF: add	Trevor Woerner	1	-4/+4
2019-01-15	riscv: move the AX25-specific implementation of flush_dcache_all	Lukas Auer	1	-0/+22
2018-12-18	riscv: ax25: Hide the ax25-specific Kconfig option	Bin Meng	1	-6/+6
2018-11-26	riscv: cache: Implement i/dcache [status, enable, disable]	Rick Chen	1	-0/+95