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2019-10-08firmware: zynqmp: create firmware headerIbai Erkiaga2-0/+2
New firmware header to place firmware specific macro and function declarations. The patch also moves the macros defining PM operations as well as some helper macros. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08firmware: zynqmp: get fw version with mailbox driverIbai Erkiaga1-2/+74
Implements the function to get PMU Firmware version using the mailbox driver or smc call based on if running SPL or not. Additionally gets version as part of the ZynqMP Firmware driver probing Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08firmware: zynqmp: Add zynqmp-power supportIbai Erkiaga1-0/+47
zynqmp-power driver for ZynqMP to handle the communication with the PMU firmware. Firmware driver just probes subnodes and power driver handles communication with PMU using the IPI mailbox driver. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08mailbox: zynqmp: ipi mailbox driverIbai Erkiaga3-0/+141
ZynqMP mailbox driver implementing IPI communication with PMU. This would allow U-Boot SPL to communicate with PMUFW to request privileged operations. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08mailbox: allow subnode for mbox regsIbai Erkiaga1-1/+10
The following patch allows the mailbox node in DT to host subnodes with mailbox definitions. If the client phandle to the mailbox is not the mailbox driver node, just checks parents as well. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08mailbox: check ops prior callingIbai Erkiaga1-2/+6
Check if request and free operations are present prior calling to the functions. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: xilinx_axiemac: Fill the phy node pointer in phydevSiva Durga Prasad Paladugu1-1/+6
This patch assings the phynode pointer to the phydev node as it is needed later in the corresponding phy driver to read phy properties from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08gpio: zynq: fix issue in set gpio output directionAshok Reddy Soma1-1/+1
This patch fixes zynq_gpio_direction() to call driver specific zynq_gpio_set_value function rather than top level gpio_set_value. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08drivers: usb: dwc3: setup phy before dwc3 core soft resetT Karthik Reddy1-2/+2
Phy setup should be done before dwc3 soft core reset as it is done in linux & this fixes unreliable detection of usb cable on host side. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08mmc: zynq_sdhci: Remove check for DM_MMC configSiva Durga Prasad Paladugu1-2/+2
The zynq_sdhci drivers depends on DM_MMC in Kconfig so no need to check for DM_MMC in the driver so this patch removes it. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: phy: Add gmiitorgmii converter supportSiva Durga Prasad Paladugu4-0/+194
This patch adds support for gmiitorgmii converter. This converter sits between the MAC and the external phy MAC <==> GMII2RGMII <==> RGMII_PHY. The ethernet driver probes this bridge and this bridge driver probes real phy driver and invokes the real phy functionalities as requested. This bridge just needs to be configured based on real phy negotiated speed and duplex. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: phy: Define init routine and register generic phy driverSiva Durga Prasad Paladugu1-0/+7
This patch define init routine for generic phy driver and registers it using phy_register as this generic phy driver also needs to be relocated incase of manual reloc. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08fpga: zynqmp: Fix second local variable declarationMichal Simek1-1/+1
No reason to define new_buf again. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08mmc: sdhci: Move ZYNQ_HISPD_BROKEN to KconfigSiva Durga Prasad Paladugu1-0/+6
This patch moves CONFIG_ZYNQ_HISPD_BROKEN to Kconfig Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: zynq_gem: Remove check for VersalSiva Durga Prasad Paladugu1-4/+0
This patch removes check for Versal platform in gem driver as it now supports clock setting through clock framework. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08clk: versal: Add clock driver supportSiva Durga Prasad Paladugu4-0/+756
This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: zynq_gem: Add new versal compatible stringSiva Durga Prasad Paladugu1-0/+1
This patch adds new versal compatible string to GEM driver for Versal platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08net: gem: Remove DECLARE_GLOBAL_DATA_PTR from gem driverMichal Simek1-2/+0
GD is not used anywhere that's why there is no reason to have this macro in the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08zynqmp: firmware: Add Xilinx ZynqMP firmware driverRajan Vaja4-0/+27
Add simple ZynqMP firmware drive to populate child nodes under zynqmp_firmware DT node. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08arm64: versal: fpga: Add PL bit stream load supportSiva Durga Prasad Paladugu4-1/+68
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-07NET: DW: fix regression for ARC boardsEugeniy Paltsev1-0/+1
The commit 642b80d256e ("net: designware: drop compatible altr, socfpga-stmmac") breaks designware ethernet for all ARC boards. It removes "altr, socfpga-stmmac" compatible from "drivers/net/designware.c" without changing compatible in the boards which use it. Fix that by adding "snps,arc-dwmac-3.70a" compatible string to "drivers/net/designware.c" and using it in ARC boards device tree. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2019-10-03dm: core: Correct bad cast in ofnode_get_addr_size_index()Simon Glass1-2/+5
At present this code passes an fdt_addr_t pointer as a u64 pointer which is not safe, since sizeof(fdt_addr_t) may be 4, e.g. with sandbox. Correct this to avoid a stack corruption problem. Fixes: e679d03b08 (core: ofnode: Add ofnode_get_addr_size_index) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-03dm: core: Correct low cell in ofnode_read_pci_addr()Simon Glass1-1/+1
This reads the low cell of the PCI address from the wrong cell. Fix it. Also fix the function that this code came from. Fixes: 9e51204527 (dm: core: Add operations on device tree references) Fixes: 4ea5243a3a (fdt: fix fdtdec_get_pci_addr() for CONFIG_PHYS_64BIT) Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-22Merge tag 'fixes-for-2019.10' of ↵Tom Rini1-1/+1
https://gitlab.denx.de/u-boot/custodians/u-boot-video.git - fix sunxi LCD clock divider - fix splash logo with DM_VIDEO and CONFIG_VIDEO_LOGO - fix splash banner output with DM_VIDEO
2019-09-21sunxi: video: HDMI: Fix LCD clock dividerMark Kettenis1-1/+1
Currently we may end up with an LCD clock divider that differs from the HDMI PHY clock divider if we can't exactly match the pixel clock. Fix this by using DIV_ROUND_UP to calculate the divider. This works since the PLL is chosen such that the resulting pixel clock is never higher than the requested pixel clock. Fixes: 1feed358ed15 ("sunxi: video: HDMI: Fix clock setup") Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2019-09-21Merge tag 'u-boot-rockchip-20190920' of ↵Tom Rini1-5/+10
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3288 tinker and evb SPL boot fail - Enable get sn from cpuid for rk3399 rockpro64 board
2019-09-19watchdog: omap_wdt: Fix WDT target reset when booted from emmcSuniel Mahesh1-1/+1
AM335X based beaglebone black target gets reset by DM converted watchdog if booted from emmc around 60sec. Fixed this by moving driver's private struct variable initialization at different places in the driver to driver's probe. Tested on Beaglebone Black. Cc: Grygorii Strashko <grygorii.strashko@ti.com> Fixes: 7659ea32 ("watchdog: omap_wdt: Convert watchdog driver to use DT and DM") Reported-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Suniel Mahesh <sunil.m@techveda.org> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
2019-09-19rtc: ds3231/ds3232: fix coding styleBiwen Li1-1/+2
The patch fixes coding style Signed-off-by: Biwen Li <biwen.li@nxp.com>
2019-09-19ram: rk3288: Initialize dram for TPL buildsJagan Teki1-5/+10
Few of the rk3288 boards like tinker, vyasa are using TPL, SPL bootchain so the dram initialization must needed during TPL stage. So add proper ifconstruct to satisfy both TPL, SPL and SPL-only bootchain boards. This eventually fixing TPL to SPL handoff, otherwise missing dram initilaztion at TPL stage would leads to SPL hang. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2019-09-16Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini3-17/+37
- Add emmc hs200 support - Few bug fixes related to serdes, I2C, ethernet, etc
2019-09-16Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini10-91/+228
- fix mvebu_a3700_spi clock prescale (Marek Behún) - unmark MXS_SPI, DEPRECATED (Lukasz) - add spi_write_then_read (Jagan) - fix SST26* flash ICs (Eugeniy) - fix soft_spi data abort (Christophe)
2019-09-16mtd: spi-nor: enable protection ops for SST26 flash seriesEugeniy Paltsev1-4/+4
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Enable protection ops for SST26 flash series which were previously enabled by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16mtd: spi-nor: add missing SST26* flash IC protection opsEugeniy Paltsev2-0/+182
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Add missing SST26* flash IC protection ops which were introduced previously by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16mtd: spi: Drop sf.cJagan Teki3-72/+1
spi_write_then_read, will manage to do the respective spi_xfer based on the tx_buf, rx_buf so drop the legacy spi_flash_read/write/cm code. Tested-by: Adam Ford <aford173@gmail.com> #da850-evm Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16mtd: spi_dataflash: Use spi read then writeJagan Teki1-9/+13
Now, we have spi_write_then_read routine that would handle spi_xfer handling based on the tx_buf and rx_buf parameters. So, replace individual flash read/write/cmd transfer call with spi_write_then_read. Cc: Egnite GmbH <info@egnite.de> Cc: Daniel Gorsulowski <daniel.gorsulowski@esd.eu> Cc: Ilko Iliev <iliev@ronetix.at> Cc: Marek Vasut <marex@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Alison Wang <alison.wang@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16spi: Add spi_write_then_readJagan Teki1-0/+24
Add support for SPI synchronous write followed by read, this is common interface call from spi-nor to spi drivers. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
2019-09-16spi: Kconfig: Unmark DEPRECATED for MXS_SPILukasz Majewski1-1/+0
MXS_SPI driver now partially converted into driver-model, so unmark the DEPRECATED option for the same. Signed-off-by: Lukasz Majewski <lukma@denx.de> [jagan: update the commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16spi: soft_spi: Fix data abort if slave is not probedChristophe Kerello1-2/+2
In case spi_get_bus_and_cs callback is used, spi bus is first probed then slave devices are probed. To avoid a data abort in soft_spi probe function, we need to check that (slave != NULL). If slave is NULL, cs_flags and clk_flags will be initialized with respectively GPIOD_ACTIVE_LOW and 0. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-16spi: mvebu_a3700_spi: Fix clock prescale computationMarek Behún1-3/+2
The prescaler value computation can yield wrong result if given 0x1f at the beginning: the value is computed to be 0x20, but the maximum value the register can hold 0x1f, so the actual stored value in this case is 0, which is obviously wrong. Set the upper bound of the value to 0x1f with the min macro. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-09-15Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini11-33/+49
- Assorted bugfixes
2019-09-13soc: ti: k3-navss-ringacc: fix k3_nav_ringacc_ring_reset_dmaVignesh Raghavendra1-1/+3
In case dma_ring_reset_quirk is not set the k3_ringacc_ring_reset_dma will just exit without ring reset. Fix it, by adding ring reset call in case dma_ring_reset_quirk is not. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-09-12watchdog: sp805_wdt: add expire_now methodThomas Schaefer1-1/+9
Add sp805_wdt_expire_now function. expire_now method is required by U_BOOT_DRIVER. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12mmc: fsl_esdhc: Add emmc hs200 supportYinbo Zhu1-15/+19
Add eMMC hs200 mode for ls1028a, ls1012a, lx2160a. This increases eMMC performance. Tuning procedure is currently not supported. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-12mmc: Kconfig: Add FSL_ESDHC_USE_PERIPHERAL_CLK optionYinbo Zhu1-1/+9
NXP fsl_esdhc controller supports two reference clocks: platform clock and peripheral clock Peripheral clock can provide higher clock frequency which is required to be used for tuning of SD UHS mode and eMMC HS200/HS400 modes. Peripheral clock is enabled by default by defining config option FSL_ESDHC_USE_PERIPHERAL_CLK if eMMC HS200/HS400 modes are supported. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-09-11rockchip: clk: rk3399: remove clk_enable()Kever Yang1-37/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3368: remove clk_enable()Kever Yang1-19/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3328: remove clk_enable()Kever Yang1-12/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11rockchip: clk: rk3288: remove clk_enable()Kever Yang1-23/+0
There is no real driver for clk enable/disable now, and we actually don't need it now, remove it so that not waste CPU cycles and code size. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-09-11usb: ohci-generic: don't probe fail if there is no clk_enable() opsKever Yang1-1/+1
Some clock driver do not have a clk_enable() call back, and we should not treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk() do not return fail if ret value is '-ENOSYS' Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2019-09-11usb: ehci-generic: don't probe fail if there is no clk_enable() opsKever Yang1-1/+1
Some clock driver do not have a clk_enable() call back, and we should not treat this as fail in ehci probe like other modules, eg. clk_enabl_bulk() do not return fail if ret value is '-ENOSYS' Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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