diff options
Diffstat (limited to 'meta-openbmc-mods/meta-ast2600')
21 files changed, 728 insertions, 138 deletions
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch index dfb11d89a..0705ab3de 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch @@ -1,4 +1,4 @@ -From ada80beb48d974f101201745657d10e72fe30b9c Mon Sep 17 00:00:00 2001 +From 041ad6cfc3d379c8e4fd271e7f9e3d8ea6ee61ac Mon Sep 17 00:00:00 2001 From: Vernon Mauery <vernon.mauery@intel.com> Date: Thu, 24 Oct 2019 14:06:33 -0700 Subject: [PATCH] Add ast2600-intel as a new board @@ -36,7 +36,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile old mode 100755 new mode 100644 -index e9d994737949..d2ad5968775e +index 786042cd8340..df844065cd4f --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -684,7 +684,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ @@ -288,10 +288,10 @@ index ee775ce5d264..8c985532afb4 100644 { efi_restore_gd(); diff --git a/arch/arm/mach-aspeed/ast2600/Kconfig b/arch/arm/mach-aspeed/ast2600/Kconfig -index 518f41b558d3..8023397cff58 100644 +index 6258b337bc3d..ffcb110c3ae3 100644 --- a/arch/arm/mach-aspeed/ast2600/Kconfig +++ b/arch/arm/mach-aspeed/ast2600/Kconfig -@@ -51,6 +51,13 @@ config TARGET_SLT_AST2600 +@@ -32,10 +32,18 @@ config TARGET_SLT_AST2600 help SLT-AST2600 is Aspeed SLT board for AST2600 chip. @@ -304,9 +304,7 @@ index 518f41b558d3..8023397cff58 100644 + endchoice - config ASPEED_SECBOOT_BL2 -@@ -71,5 +78,6 @@ source "board/aspeed/ncsi_ast2600a0/Kconfig" - source "board/aspeed/ncsi_ast2600a1/Kconfig" + source "board/aspeed/evb_ast2600/Kconfig" source "board/aspeed/fpga_ast2600/Kconfig" source "board/aspeed/slt_ast2600/Kconfig" +source "board/aspeed/ast2600_intel/Kconfig" diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0002-AST2600-Enable-host-searial-port-clock-configuration.patch index 915b0197f..cd09ab4f0 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0021-AST2600-Enable-host-searial-port-clock-configuration.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0002-AST2600-Enable-host-searial-port-clock-configuration.patch @@ -1,4 +1,4 @@ -From c2e2496dfd8cde56e32274b11968185a77f40736 Mon Sep 17 00:00:00 2001 +From 816ae827f387922e31281c8b10988870ce9e0294 Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Tue, 10 Dec 2019 14:58:10 +0800 Subject: [PATCH] AST2600: Enable host searial port clock configuration in @@ -14,14 +14,14 @@ by default is 24Mhz. Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> --- - board/aspeed/ast2600_intel/intel.c | 35 +++++++++++++++++++++++++++++++++++ + board/aspeed/ast2600_intel/intel.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index a02e246d0d81..eb9b3959625e 100644 +index 4a40a050c3da..d1ac8651ac6c 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -36,9 +36,44 @@ int gpio_abort(void) +@@ -39,9 +39,44 @@ int gpio_abort(void) } #define SCU_BASE 0x1E6E2000 @@ -67,5 +67,5 @@ index a02e246d0d81..eb9b3959625e 100644 return 0; } -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch index 326f36df1..a036b91fc 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0003-ast2600-intel-layout-environment-addr.patch @@ -1,4 +1,4 @@ -From 3195e1ec2d772d5e4c16ae5b60c294086cfc17be Mon Sep 17 00:00:00 2001 +From fdb55afe15fdbba33782d01a77bbf994470f40b4 Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Thu, 12 Dec 2019 12:54:18 +0800 Subject: [PATCH] ast2600: intel-layout-environment-addr @@ -9,12 +9,12 @@ Both kernel and u-boot work at the area /dev/mtd/u-boot-env Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - common/board_r.c | 13 ++++++++++--- + common/board_r.c | 11 +++++++++-- include/configs/aspeed-common.h | 11 ++++++++++- - 2 files changed, 20 insertions(+), 4 deletions(-) + 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/common/board_r.c b/common/board_r.c -index 472987d5d52f..b665d0e30262 100644 +index 472987d5d52f..434c0df45c85 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -433,10 +433,17 @@ static int should_load_env(void) @@ -22,8 +22,6 @@ index 472987d5d52f..b665d0e30262 100644 { /* initialize environment */ - if (should_load_env()) -- env_relocate(); -- else + if (should_load_env()) { + /* + * try again, in case the environment failed to load the first @@ -31,7 +29,8 @@ index 472987d5d52f..b665d0e30262 100644 + */ + if (!gd->env_valid) + env_init(); -+ env_relocate(); + env_relocate(); +- else + } else { set_default_env(NULL, 0); + } @@ -39,10 +38,10 @@ index 472987d5d52f..b665d0e30262 100644 env_set_hex("fdtcontroladdr", (unsigned long)map_to_sysmem(gd->fdt_blob)); diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h -index cdbffc97a223..6065ec58db0a 100644 +index 8718b50f9ebe..70590067dbcf 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h -@@ -65,9 +65,18 @@ +@@ -73,9 +73,18 @@ #endif #ifndef CONFIG_ENV_OFFSET @@ -63,5 +62,5 @@ index cdbffc97a223..6065ec58db0a 100644 /* -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch index d5bd4a2b1..ec4b6be09 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch @@ -1,4 +1,4 @@ -From c1561193296d04dd8bd06adca43edac814058367 Mon Sep 17 00:00:00 2001 +From 0732dd21869418b4d437b8d1aef239d5348fc94d Mon Sep 17 00:00:00 2001 From: Kuiying Wang <kuiying.wang@intel.com> Date: Fri, 3 Jan 2020 12:52:29 +0800 Subject: [PATCH] Enable interrupt in u-boot. @@ -14,18 +14,18 @@ Testedby: Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - Kconfig | 14 +++ + Kconfig | 14 ++ arch/arm/lib/stack.c | 9 ++ - arch/arm/lib/vectors.S | 30 +++++- + arch/arm/lib/vectors.S | 30 ++++- board/aspeed/ast2600_intel/ast-espi.c | 3 +- - board/aspeed/ast2600_intel/ast-irq.c | 185 +++++++++++++++++----------------- + board/aspeed/ast2600_intel/ast-irq.c | 185 +++++++++++++------------- board/aspeed/ast2600_intel/ast-irq.h | 8 -- board/aspeed/ast2600_intel/intel.c | 1 - 7 files changed, 145 insertions(+), 105 deletions(-) delete mode 100644 board/aspeed/ast2600_intel/ast-irq.h diff --git a/Kconfig b/Kconfig -index 305b265ed713..a6f68cd13d54 100644 +index c3dfa8de47c8..b62bcdbccf1e 100644 --- a/Kconfig +++ b/Kconfig @@ -239,6 +239,20 @@ config BUILD_TARGET @@ -551,10 +551,10 @@ index 9957f2baa7ff..000000000000 - -#endif diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index ac108c3a066c..22a377d2cb77 100644 +index 14a20b27e178..d03a446846bc 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -209,7 +209,6 @@ static void timer_handler(void *regs) +@@ -239,7 +239,6 @@ static void timer_handler(void *regs) printf("+"); } @@ -563,5 +563,5 @@ index ac108c3a066c..22a377d2cb77 100644 { /* This is called before relocation; beware! */ -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch index 720d165c5..612a104b5 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0006-SPI-Quad-IO-Mode.patch @@ -1,4 +1,4 @@ -From fd0768e6a63a25fdc87596036a5cbf82a88a1eb6 Mon Sep 17 00:00:00 2001 +From ddd0ebfaf667f2fd36ed2f8d2d8456dbc6acdaa8 Mon Sep 17 00:00:00 2001 From: arun-pm <arun.p.m@linux.intel.com> Date: Fri, 29 Nov 2019 00:19:09 +0530 Subject: [PATCH] SPI Quad IO Mode @@ -37,10 +37,10 @@ index 9a15e204f83b..1f14753056ee 100644 }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c -index 3b0a910d3fca..d6b949170570 100644 +index 5882eab2e3fc..42546f4d222a 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = { +@@ -189,7 +189,12 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, @@ -51,11 +51,11 @@ index 3b0a910d3fca..d6b949170570 100644 + * back(Note:- Certain other chips having same name(n25q00) but different part number has no issues). + */ + { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | NO_CHIP_ERASE) }, + { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, - #endif diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c -index 18d4c2fa098e..6efb8c4e3c65 100644 +index f93200f8f67e..8ac6e40524fe 100644 --- a/drivers/spi/aspeed_spi.c +++ b/drivers/spi/aspeed_spi.c @@ -17,6 +17,9 @@ @@ -68,13 +68,13 @@ index 18d4c2fa098e..6efb8c4e3c65 100644 struct aspeed_spi_regs { u32 conf; /* 0x00 CE Type Setting */ -@@ -1037,6 +1040,19 @@ static int aspeed_spi_bind(struct udevice *bus) +@@ -1059,6 +1062,19 @@ static int aspeed_spi_bind(struct udevice *bus) return 0; } +static int aspeed_get_max_freq(void) +{ -+ u32 rev_id = readl(ASPEED_REVISION_ID); ++ u32 rev_id = readl(ASPEED_REVISION_ID0); + + /*Limit max spi frequency less than 50MHz on AST2600-A0 due + * to FWSPICLK signal quality issue. @@ -88,7 +88,7 @@ index 18d4c2fa098e..6efb8c4e3c65 100644 static int aspeed_spi_probe(struct udevice *bus) { struct resource res_regs, res_ahb; -@@ -1067,7 +1083,7 @@ static int aspeed_spi_probe(struct udevice *bus) +@@ -1089,7 +1105,7 @@ static int aspeed_spi_probe(struct udevice *bus) clk_free(&hclk); priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch index 2a2d1054a..c4b8a00ef 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0007-ast2600-Override-OTP-strap-settings.patch @@ -1,4 +1,4 @@ -From 6f9d529b616ce84271ccd2584b9bcd8d13ab57de Mon Sep 17 00:00:00 2001 +From 844e425a503c56bd84dbfe5396c5f8f9b4284e6d Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Wed, 29 Jan 2020 14:55:44 -0800 Subject: [PATCH] ast2600: Override OTP strap settings @@ -8,11 +8,11 @@ Also, this commit disables SoC debug interface. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - arch/arm/mach-aspeed/ast2600/platform.S | 26 ++++++++++++++++++++++--- - 1 file changed, 23 insertions(+), 3 deletions(-) + arch/arm/mach-aspeed/ast2600/platform.S | 24 ++++++++++++++++++++++-- + 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index f193c66cd04b..997670b66bdc 100644 +index f96ef1f0dac4..3b6f91a60c3d 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -44,7 +44,9 @@ @@ -25,7 +25,7 @@ index f193c66cd04b..997670b66bdc 100644 #define AST_SCU_CA7_PARITY_CHK (AST_SCU_BASE + 0x820) #define AST_SCU_CA7_PARITY_CLR (AST_SCU_BASE + 0x824) #define AST_SCU_MMIO_DEC_SET (AST_SCU_BASE + 0xC24) -@@ -173,6 +175,26 @@ do_primary_core_setup: +@@ -175,6 +177,26 @@ do_primary_core_setup: /* unlock system control unit */ scu_unlock @@ -52,7 +52,7 @@ index f193c66cd04b..997670b66bdc 100644 /* identify AST2600 A0/A1 */ ldr r0, =AST_SCU_REV_ID ldr r0, [r0] -@@ -262,19 +284,17 @@ skip_fill_wip_bit: +@@ -277,7 +299,6 @@ skip_fill_wip_bit: ldr r1, =AST_FMC_WDT1_CTRL_MODE str r0, [r1] @@ -60,12 +60,7 @@ index f193c66cd04b..997670b66bdc 100644 /* disable UART-based SoC Debug Interface UART5 and P2A bridge*/ ldr r0, =AST_SCU_DEBUG_CTRL ldr r1, [r0] - orr r1, #0x03 - str r1, [r0] -- -+ - /* disable UART-based SoC Debug Interface UART1 and LPC2AHB bridge */ - ldr r0, =AST_SCU_DEBUG_CTRL2 +@@ -289,7 +310,6 @@ skip_fill_wip_bit: ldr r1, [r0] orr r1, #0x0A str r1, [r0] diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch index f47092eaa..a506f3028 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch @@ -1,4 +1,4 @@ -From f1bfa10fefa992c7032e0c32647543bb2a8dc90f Mon Sep 17 00:00:00 2001 +From f545610f26089e78e71469e9006e3337670af0f4 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Tue, 31 Mar 2020 13:28:31 -0700 Subject: [PATCH] AST2600: Disable DMA arbitration options on MAC1 and MAC2 @@ -17,7 +17,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index 997670b66bdc..6b447845fe26 100644 +index 3b6f91a60c3d..eac52db538b0 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -57,6 +57,12 @@ @@ -33,10 +33,10 @@ index 997670b66bdc..6b447845fe26 100644 #define AST_GPIO_BASE (0x1E780000) #define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) -@@ -229,6 +235,18 @@ wait_lock: - b 1f +@@ -244,6 +250,18 @@ wait_lock: + bne 2f - 0: + 1: + /* disable DMA arbitration on MAC1 (A1 bug) */ + ldr r0, =AST_MAC1_CTRL2 + ldr r1, [r0] @@ -49,7 +49,7 @@ index 997670b66bdc..6b447845fe26 100644 + orr r1, #0x18000000 + str r1, [r0] + - /* LPC/eSPI mode selection (A1 only) */ + /* LPC/eSPI mode selection by SW (AST2600/AST2620 A1 only) */ ldr r0, =AST_GPIOYZ_DATA_VALUE ldr r0, [r0] -- diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch index cf13a17f2..e998ae42f 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch @@ -1,4 +1,4 @@ -From bd4eb78dc71529342e5d0b784731c412cf747acc Mon Sep 17 00:00:00 2001 +From 97fc99c77c68ec6b71354786f94a80a26adde389 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Mon, 20 Apr 2020 10:42:05 -0700 Subject: [PATCH] Fix timer support @@ -10,8 +10,8 @@ commit adds the timer interrupt flag clearing logic. Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- - board/aspeed/ast2600_intel/ast-timer.c | 69 ++++++++++++++++++++-------------- - board/aspeed/ast2600_intel/intel.c | 13 ++++--- + board/aspeed/ast2600_intel/ast-timer.c | 69 +++++++++++++++----------- + board/aspeed/ast2600_intel/intel.c | 13 ++--- 2 files changed, 48 insertions(+), 34 deletions(-) diff --git a/board/aspeed/ast2600_intel/ast-timer.c b/board/aspeed/ast2600_intel/ast-timer.c @@ -120,10 +120,10 @@ index cf8c69aba5d3..d98ec9238e15 100644 + AST_TIMER_BASE + TIMER_CONTROL); } diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index 47e5ad21d66d..befeaff0a953 100644 +index ebf883144418..7c005fb323e6 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -219,16 +219,14 @@ void enable_onboard_tpm(void) +@@ -249,16 +249,14 @@ void enable_onboard_tpm(void) AST_GPIO_BASE | GPIO_000); } @@ -142,7 +142,7 @@ index 47e5ad21d66d..befeaff0a953 100644 arch_interrupt_init_early(); set_gpio_default_state(); -@@ -243,11 +241,9 @@ int board_early_init_f(void) +@@ -273,11 +271,9 @@ int board_early_init_f(void) return 0; } @@ -154,7 +154,7 @@ index 47e5ad21d66d..befeaff0a953 100644 enable_onboard_tpm(); -@@ -255,8 +251,13 @@ int board_early_init_r(void) +@@ -285,8 +281,13 @@ int board_early_init_r(void) } extern void espi_init(void); @@ -169,5 +169,5 @@ index 47e5ad21d66d..befeaff0a953 100644 return 0; -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch index f446d797a..6a37f7b72 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch @@ -1,4 +1,4 @@ -From 1fbd857e2ff5396ea057f686cbd01c6db4328316 Mon Sep 17 00:00:00 2001 +From b26b11483b006f603e0134551bfb1238e0980972 Mon Sep 17 00:00:00 2001 From: AppaRao Puli <apparao.puli@linux.intel.com> Date: Mon, 20 Apr 2020 11:08:22 -0700 Subject: [PATCH] KCS driver support in uBoot @@ -29,8 +29,8 @@ Signed-off-by: James Feist <james.feist@linux.intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- board/aspeed/ast2600_intel/Makefile | 1 + - board/aspeed/ast2600_intel/ast-kcs.c | 418 +++++++++++++++++++++++++++++++++++ - board/aspeed/ast2600_intel/ast-kcs.h | 112 ++++++++++ + board/aspeed/ast2600_intel/ast-kcs.c | 418 +++++++++++++++++++++++++++ + board/aspeed/ast2600_intel/ast-kcs.h | 112 +++++++ board/aspeed/ast2600_intel/intel.c | 4 + 4 files changed, 535 insertions(+) create mode 100644 board/aspeed/ast2600_intel/ast-kcs.c @@ -588,10 +588,10 @@ index 000000000000..e9b949eccf69 + u8 data_out[MAX_KCS_PKT_SIZE]; +}; diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index befeaff0a953..6ac24beb930b 100644 +index 7c005fb323e6..b3d2fb313561 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -251,6 +251,7 @@ int board_early_init_r(void) +@@ -281,6 +281,7 @@ int board_early_init_r(void) } extern void espi_init(void); @@ -599,7 +599,7 @@ index befeaff0a953..6ac24beb930b 100644 extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, void *cookie); int board_late_init(void) -@@ -260,6 +261,9 @@ int board_late_init(void) +@@ -290,6 +291,9 @@ int board_late_init(void) timer_enable(0, ONE_SEC_IN_USEC, timer_callback, (void *)0); espi_init(); @@ -610,5 +610,5 @@ index befeaff0a953..6ac24beb930b 100644 } -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch index 7d7b450a8..04baccf66 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch @@ -1,4 +1,4 @@ -From 2d0a3aff4c4aa3a764958579ed10a3aab43a7d8a Mon Sep 17 00:00:00 2001 +From e027384b44aff330375477556eed10c326ad1c48 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Mon, 27 Apr 2020 12:40:01 -0700 Subject: [PATCH] Add a workaround to cover UART interrupt bug in AST2600 A0 @@ -13,10 +13,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index 6ac24beb930b..ad5ab7632447 100644 +index b3d2fb313561..0d1ce69b6e53 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c -@@ -221,7 +221,19 @@ void enable_onboard_tpm(void) +@@ -251,7 +251,19 @@ void enable_onboard_tpm(void) static void timer_callback(void *cookie) { @@ -37,7 +37,7 @@ index 6ac24beb930b..ad5ab7632447 100644 } int board_early_init_f(void) -@@ -256,9 +268,13 @@ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, +@@ -286,9 +298,13 @@ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, void *cookie); int board_late_init(void) { @@ -54,5 +54,5 @@ index 6ac24beb930b..ad5ab7632447 100644 if (read_ffuj()) -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-system-reset-status-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-system-reset-status-support.patch index 89a8808eb..1b0d4d95b 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-system-reset-status-support.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0016-Add-system-reset-status-support.patch @@ -1,4 +1,4 @@ -From 0a2511d407ad9294b8c08f5228d85e042c104aaa Mon Sep 17 00:00:00 2001 +From ea8f8aa37182b66893ac9afcbbb4d5043b3b4166 Mon Sep 17 00:00:00 2001 From: Yong Li <yong.b.li@linux.intel.com> Date: Tue, 9 Apr 2019 14:42:05 +0800 Subject: [PATCH] Add system reset status support @@ -13,12 +13,12 @@ Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> --- arch/arm/mach-aspeed/ast2600/scu_info.c | 4 ++ - board/aspeed/ast2600_intel/intel.c | 65 +++++++++++++++++++++++++++++++++ + board/aspeed/ast2600_intel/intel.c | 65 +++++++++++++++++++++++++ include/asm-generic/global_data.h | 3 ++ 3 files changed, 72 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/scu_info.c b/arch/arm/mach-aspeed/ast2600/scu_info.c -index 2ee88b4dd39b..2cc6c3652bab 100644 +index fe26f743c0ca..18514c812018 100644 --- a/arch/arm/mach-aspeed/ast2600/scu_info.c +++ b/arch/arm/mach-aspeed/ast2600/scu_info.c @@ -9,6 +9,8 @@ @@ -30,7 +30,7 @@ index 2ee88b4dd39b..2cc6c3652bab 100644 /* SoC mapping Table */ #define SOC_ID(str, rev) { .name = str, .rev_id = rev, } -@@ -237,6 +239,8 @@ void aspeed_print_sysrst_info(void) +@@ -263,6 +265,8 @@ void aspeed_print_sysrst_info(void) writel(SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); } } @@ -40,7 +40,7 @@ index 2ee88b4dd39b..2cc6c3652bab 100644 #define SOC_FW_INIT_DRAM BIT(7) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c -index 05872b439361..95e5492009d7 100644 +index 0d1ce69b6e53..849e81ff3fef 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c @@ -5,6 +5,7 @@ @@ -51,7 +51,7 @@ index 05872b439361..95e5492009d7 100644 /* use GPIOC0 on intel boards */ #define FFUJ_GPIO "gpio@1e78000016" -@@ -274,6 +275,65 @@ int board_early_init_r(void) +@@ -292,6 +293,65 @@ int board_early_init_r(void) return 0; } @@ -117,7 +117,7 @@ index 05872b439361..95e5492009d7 100644 extern void espi_init(void); extern void kcs_init(void); extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, -@@ -283,12 +343,17 @@ int board_late_init(void) +@@ -301,12 +361,17 @@ int board_late_init(void) #define SCU_014 0x014 /* Silicon Revision ID */ #define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ #define ONE_MSEC_IN_USEC 1000 @@ -150,5 +150,5 @@ index 78dcf40bff48..fa51e384520f 100644 #endif -- -2.7.4 +2.17.1 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch index da69791ea..66a1b564e 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0018-Add-a-workaround-to-cover-VGA-memory-size-bug-in-A0.patch @@ -1,4 +1,4 @@ -From 1333a1ff082cbaec4a44cefaf84d1bcc03ba1510 Mon Sep 17 00:00:00 2001 +From 2f4d7260a4ab0eb33d1145cd640019aa1fa1414a Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Thu, 18 Jun 2020 15:08:57 -0700 Subject: [PATCH] Add a workaround to cover VGA memory size bug in A0 @@ -13,10 +13,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index 6b447845fe26..55b867ff1b17 100644 +index eac52db538b0..cf709aaa5d98 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -210,6 +210,12 @@ do_primary_core_setup: +@@ -212,6 +212,12 @@ do_primary_core_setup: bne 0f @@ -29,10 +29,10 @@ index 6b447845fe26..55b867ff1b17 100644 /* tune up CPU clocks (A0 only) */ ldr r0, =AST_SCU_HW_STRAP1 ldr r1, [r0] -@@ -235,6 +241,17 @@ wait_lock: - b 1f +@@ -250,6 +256,17 @@ wait_lock: + bne 2f - 0: + 1: + /* set VGA memory size to 16MB (A1 only) */ + ldr r0, =AST_SCU_HW_STRAP1_CLR + movw r1, #0x4000 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch index ea7650f8b..26c83f8d6 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0019-Apply-WDT1-2-reset-mask-to-reset-needed-controller.patch @@ -1,4 +1,4 @@ -From a56e138569ce7b37285d4c2f2b4ef4082ab2a283 Mon Sep 17 00:00:00 2001 +From 783ef5212c5efc0561361fd779f1be3b047aee74 Mon Sep 17 00:00:00 2001 From: Suryakanth Sekar <suryakanth.sekar@linux.intel.com> Date: Thu, 18 Jun 2020 05:32:48 +0530 Subject: [PATCH] Apply WDT1-2 reset mask to reset needed controller @@ -61,7 +61,7 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com> 1 file changed, 22 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index 55b867ff1b17..cd8a57edd76b 100644 +index cf709aaa5d98..027265593f03 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -63,6 +63,14 @@ @@ -79,10 +79,10 @@ index 55b867ff1b17..cd8a57edd76b 100644 #define AST_GPIO_BASE (0x1E780000) #define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) -@@ -277,6 +285,20 @@ wait_lock: +@@ -292,6 +300,20 @@ wait_lock: str r1, [r0] - 1: + 2: + /* disable eSPI, LPC and PWM resets on WDT1 reset */ + ldr r0, =AST_WDT1_RESET_MASK2 + ldr r1, [r0] diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch index da7889be6..e62403413 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch @@ -1,4 +1,4 @@ -From 473b1990ecb578b6dc5d3347dc0ab8f7d5609137 Mon Sep 17 00:00:00 2001 +From 385629a99a8d07182812264f2868d5f85fb711e0 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Wed, 16 Sep 2020 13:25:36 -0700 Subject: [PATCH] Add WDT to u-boot to cover booting failures @@ -20,7 +20,7 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 7 files changed, 116 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index cd8a57edd76b..08f33a9f1a17 100644 +index 027265593f03..e57bd325277f 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -64,6 +64,9 @@ @@ -33,7 +33,7 @@ index cd8a57edd76b..08f33a9f1a17 100644 #define AST_WDT1_RESET_MASK1 (AST_WDT1_BASE + 0x01C) #define AST_WDT1_RESET_MASK2 (AST_WDT1_BASE + 0x020) -@@ -313,6 +316,18 @@ wait_lock: +@@ -328,6 +331,18 @@ wait_lock: ldr r1, =AST_SCU_CA7_PARITY_CHK str r0, [r1] @@ -150,7 +150,7 @@ index 4d4248f234fb..90687092e1ae 100644 from += len; to += len; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c -index 1793a9e1f560..2ba5e5d65f4a 100644 +index a8f5b6158241..69dfc7f21698 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -20,6 +20,7 @@ @@ -161,7 +161,7 @@ index 1793a9e1f560..2ba5e5d65f4a 100644 #include "sf_internal.h" -@@ -425,6 +426,10 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, +@@ -429,6 +430,10 @@ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, unsigned long timebase; int ret; @@ -300,12 +300,12 @@ index c2dc3cf548d2..811ead41bb95 100644 return 0; } diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h -index 255901ff0ea8..0797cd4febed 100755 +index 70590067dbcf..0eaf76b50b39 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h -@@ -18,6 +18,8 @@ - #define CONFIG_IPADDR 192.168.0.45 - #define CONFIG_SERVERIP 192.168.0.81 +@@ -20,6 +20,8 @@ + + #define CONFIG_STANDALONE_LOAD_ADDR 0x83000000 +#define CONFIG_HW_WATCHDOG + diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch index 23fc22ea7..1191a6077 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch @@ -1,4 +1,4 @@ -From 5ca28a9259d084440879be48ef4b4d6716794281 Mon Sep 17 00:00:00 2001 +From 438ff3a8db6718bb137dccaafa707f8275407742 Mon Sep 17 00:00:00 2001 From: Vikram Bodireddy <vikram.bodireddy@intel.com> Date: Mon, 22 Feb 2021 17:22:16 +0530 Subject: [PATCH] ast2600-PFR-platform-EXTRST-reset-mask-selection @@ -12,11 +12,11 @@ to be reset so that Host functionality would be intact. Signed-off-by: Chalapathi Venkataramashetty <chalapathix.venkataramashetty@intel.com> Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com> --- - arch/arm/mach-aspeed/ast2600/platform.S | 11 +++++++++++ - 1 file changed, 11 insertions(+) + arch/arm/mach-aspeed/ast2600/platform.S | 12 ++++++++++++ + 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index ecc9fd33d1..8c40515b76 100644 +index bdc0884de1bd..d7115c96f117 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -39,6 +39,8 @@ @@ -28,14 +28,15 @@ index ecc9fd33d1..8c40515b76 100644 #define AST_SCU_DEBUG_CTRL (AST_SCU_BASE + 0x0C8) #define AST_SCU_DEBUG_CTRL2 (AST_SCU_BASE + 0x0D8) #define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200) -@@ -285,6 +287,15 @@ wait_lock: +@@ -303,6 +305,16 @@ wait_lock: str r1, [r0] - 1: + 2: + /* SCU060:EXTRST1# reset mask selection */ + ldr r0, =AST_SCU_EXTRST_SEL1 + ldr r1, =0x6FF1FF5 + str r1, [r0] ++ + /* SCU070:EXTRST2# reset mask selection */ + ldr r0, =AST_SCU_EXTRST_SEL2 + ldr r1, =0x3FFFFF7 diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-Enable-PCIe-L1-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch index 8cc95174f..b01b96e16 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0025-Enable-PCIe-L1-support.patch +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0026-Enable-PCIe-L1-support.patch @@ -1,4 +1,4 @@ -From 1f95d121b4a11444bffd0494bcfff1986e0905b6 Mon Sep 17 00:00:00 2001 +From 8534fb50dfe7c4e1c042843ded54c4ed23ee7bc2 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> Date: Tue, 8 Jan 2019 13:33:15 -0800 Subject: [PATCH] Enable PCIe L1 support @@ -11,10 +11,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S -index cd8a57edd76b..ecc9fd33d125 100644 +index d7115c96f117..803ff94c4fc0 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S -@@ -299,6 +299,20 @@ wait_lock: +@@ -329,6 +329,20 @@ wait_lock: bic r1, r2 str r1, [r0] diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch new file mode 100644 index 000000000..ac7262f2c --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0030-Add-Aspeed-PWM-uclass-driver.patch @@ -0,0 +1,576 @@ +From b68b7c30fa3331642e321d150017d431d8cf6f6d Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Mon, 17 May 2021 13:11:24 -0700 +Subject: [PATCH] Add Aspeed PWM uclass driver + +This commit adds Aspeed PWM uclass driver to set default FAN speed +in u-boot. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/dts/ast2600-intel.dts | 11 ++ + arch/arm/dts/ast2600.dtsi | 88 ++++++++++++ + board/aspeed/ast2600_intel/intel.c | 49 +++++++ + drivers/pinctrl/aspeed/pinctrl_ast2600.c | 130 ++++++++++++++++- + drivers/pwm/Kconfig | 8 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/aspeed_pwm.c | 175 +++++++++++++++++++++++ + 7 files changed, 461 insertions(+), 1 deletion(-) + create mode 100644 drivers/pwm/aspeed_pwm.c + +diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts +index 5243d1a0afc3..79356d8b7a64 100644 +--- a/arch/arm/dts/ast2600-intel.dts ++++ b/arch/arm/dts/ast2600-intel.dts +@@ -53,6 +53,17 @@ + }; + }; + ++&pwm { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default ++ &pinctrl_pwm2_default &pinctrl_pwm3_default ++ &pinctrl_pwm4_default &pinctrl_pwm5_default ++ &pinctrl_pwm12g1_default &pinctrl_pwm13g1_default ++ &pinctrl_pwm14g1_default &pinctrl_pwm15g1_default>; ++}; ++ + &gpio0 { + status = "okay"; + }; +diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi +index e619f7118886..44ec6655fee7 100644 +--- a/arch/arm/dts/ast2600.dtsi ++++ b/arch/arm/dts/ast2600.dtsi +@@ -265,6 +265,14 @@ + #size-cells = <1>; + ranges; + ++ pwm: pwm-controller@1e610000 { ++ compatible = "aspeed,ast2600-pwm"; ++ reg = <0x1e610000 0x100>; ++ clocks = <&scu ASPEED_CLK_AHB>; ++ resets = <&rst ASPEED_RESET_PWM>; ++ status = "disabled"; ++ }; ++ + syscon: syscon@1e6e2000 { + compatible = "aspeed,g6-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1000>; +@@ -1589,6 +1597,86 @@ + groups = "PWM7"; + }; + ++ pinctrl_pwm8g1_default: pwm8g1_default { ++ function = "PWM8G1"; ++ groups = "PWM8G1"; ++ }; ++ ++ pinctrl_pwm9g1_default: pwm9g1_default { ++ function = "PWM9G1"; ++ groups = "PWM9G1"; ++ }; ++ ++ pinctrl_pwm10g1_default: pwm10g1_default { ++ function = "PWM10G1"; ++ groups = "PWM10G1"; ++ }; ++ ++ pinctrl_pwm11g1_default: pwm11g1_default { ++ function = "PWM11G1"; ++ groups = "PWM11G1"; ++ }; ++ ++ pinctrl_pwm12g1_default: pwm12g1_default { ++ function = "PWM12G1"; ++ groups = "PWM12G1"; ++ }; ++ ++ pinctrl_pwm13g1_default: pwm13g1_default { ++ function = "PWM13G1"; ++ groups = "PWM13G1"; ++ }; ++ ++ pinctrl_pwm14g1_default: pwm14g1_default { ++ function = "PWM14G1"; ++ groups = "PWM14G1"; ++ }; ++ ++ pinctrl_pwm15g1_default: pwm15g1_default { ++ function = "PWM15G1"; ++ groups = "PWM15G1"; ++ }; ++ ++ pinctrl_pwm8g0_default: pwm8g0_default { ++ function = "PWM8G0"; ++ groups = "PWM8G0"; ++ }; ++ ++ pinctrl_pwm9g0_default: pwm9g0_default { ++ function = "PWM9G0"; ++ groups = "PWM9G0"; ++ }; ++ ++ pinctrl_pwm10g0_default: pwm10g0_default { ++ function = "PWM10G0"; ++ groups = "PWM10G0"; ++ }; ++ ++ pinctrl_pwm11g0_default: pwm11g0_default { ++ function = "PWM11G0"; ++ groups = "PWM11G0"; ++ }; ++ ++ pinctrl_pwm12g0_default: pwm12g0_default { ++ function = "PWM12G0"; ++ groups = "PWM12G0"; ++ }; ++ ++ pinctrl_pwm13g0_default: pwm13g0_default { ++ function = "PWM13G0"; ++ groups = "PWM13G0"; ++ }; ++ ++ pinctrl_pwm14g0_default: pwm14g0_default { ++ function = "PWM14G0"; ++ groups = "PWM14G0"; ++ }; ++ ++ pinctrl_pwm15g0_default: pwm15g0_default { ++ function = "PWM15G0"; ++ groups = "PWM15G0"; ++ }; ++ + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; +diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c +index ec6b70ae6659..11b8d4dd8360 100644 +--- a/board/aspeed/ast2600_intel/intel.c ++++ b/board/aspeed/ast2600_intel/intel.c +@@ -8,6 +8,7 @@ + #include <led.h> + #include <malloc.h> + #include <wdt.h> ++#include <pwm.h> + + #define SYS_PWR_RESET_FLAG BIT(0) /* from scu_info.c */ + #define WATCHDOG_RESET_BIT BIT(20) +@@ -426,6 +427,53 @@ static void mailbox_init(void) + } + } + ++struct pwm_setting { ++ uint channel; ++ uint duty_pct; ++}; ++ ++static void pwm_init(void) ++{ ++#define NSEC_PER_SEC 1000000000L ++#define PWM_TARGET_FREQ 25000 ++#define PWM_TICK_NS (NSEC_PER_SEC / PWM_TARGET_FREQ) ++#define PWM_TICK_1PCT_NS (PWM_TICK_NS / 100) ++ const struct pwm_setting settings[] = { ++ {0, 65}, ++ {1, 65}, ++ {2, 65}, ++ {3, 65}, ++ {4, 65}, ++ {5, 65}, ++ {12, 65}, ++ {13, 65}, ++ {14, 65}, ++ {15, 65}, ++ }; ++ struct udevice *dev; ++ int ret, setting_size, i; ++ ++ ret = uclass_first_device(UCLASS_PWM, &dev); ++ if (ret) { ++ debug("Can't find PWM controller: %d\n", ret); ++ return; ++ } ++ ++ setting_size = sizeof(settings) / sizeof(settings[0]); ++ ++ for (i = 0; i < setting_size; i++) { ++ ret = pwm_set_config(dev, settings[i].channel, PWM_TICK_NS, ++ settings[i].duty_pct * PWM_TICK_1PCT_NS); ++ if (!ret) { ++ ret = pwm_set_enable(dev, settings[i].channel, true); ++ if (ret) ++ debug("PWM enabling failed: %d\n", ret); ++ } else { ++ debug("PWM configure failed: %d\n", ret); ++ } ++ } ++} ++ + int board_early_init_f(void) + { + /* This is called before relocation; beware! */ +@@ -613,6 +661,7 @@ int board_late_init(void) + timer_callback, (void *)1); + #endif + ++ pwm_init(); + espi_init(); + + /* Add reset reason to bootargs */ +diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c +index 8a77a5d31556..980667f84e30 100644 +--- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c ++++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c +@@ -326,6 +326,110 @@ static struct aspeed_sig_desc pcie1rc_link[] = { + { 0x500, BIT(24), 0 }, //dedicate rc reset + }; + ++static struct aspeed_sig_desc pwm0[] = { ++ { 0x41C, BIT(16), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm1[] = { ++ { 0x41C, BIT(17), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm2[] = { ++ { 0x41C, BIT(18), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm3[] = { ++ { 0x41C, BIT(19), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm4[] = { ++ { 0x41C, BIT(20), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm5[] = { ++ { 0x41C, BIT(21), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm6[] = { ++ { 0x41C, BIT(22), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm7[] = { ++ { 0x41C, BIT(23), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm8g1[] = { ++ { 0x41C, BIT(24), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm9g1[] = { ++ { 0x41C, BIT(25), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm10g1[] = { ++ { 0x41C, BIT(26), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm11g1[] = { ++ { 0x41C, BIT(27), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm12g1[] = { ++ { 0x41C, BIT(28), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm13g1[] = { ++ { 0x41C, BIT(29), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm14g1[] = { ++ { 0x41C, BIT(30), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm15g1[] = { ++ { 0x41C, BIT(31), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm8g0[] = { ++ { 0x414, BIT(8), 1 }, ++ { 0x4B4, BIT(8), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm9g0[] = { ++ { 0x414, BIT(9), 1 }, ++ { 0x4B4, BIT(9), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm10g0[] = { ++ { 0x414, BIT(10), 1 }, ++ { 0x4B4, BIT(10), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm11g0[] = { ++ { 0x414, BIT(11), 1 }, ++ { 0x4B4, BIT(11), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm12g0[] = { ++ { 0x414, BIT(12), 1 }, ++ { 0x4B4, BIT(12), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm13g0[] = { ++ { 0x414, BIT(13), 1 }, ++ { 0x4B4, BIT(13), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm14g0[] = { ++ { 0x414, BIT(14), 1 }, ++ { 0x4B4, BIT(14), 0 }, ++}; ++ ++static struct aspeed_sig_desc pwm15g0[] = { ++ { 0x414, BIT(15), 1 }, ++ { 0x4B4, BIT(15), 0 }, ++}; ++ + static const struct aspeed_group_config ast2600_groups[] = { + { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, + { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, +@@ -383,7 +487,31 @@ static const struct aspeed_group_config ast2600_groups[] = { + { "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link }, + { "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link }, + { "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link }, +- { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link }, ++ { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link }, ++ { "PWM0", ARRAY_SIZE(pwm0), pwm0 }, ++ { "PWM1", ARRAY_SIZE(pwm1), pwm1 }, ++ { "PWM2", ARRAY_SIZE(pwm2), pwm2 }, ++ { "PWM3", ARRAY_SIZE(pwm3), pwm3 }, ++ { "PWM4", ARRAY_SIZE(pwm4), pwm4 }, ++ { "PWM5", ARRAY_SIZE(pwm5), pwm5 }, ++ { "PWM6", ARRAY_SIZE(pwm6), pwm6 }, ++ { "PWM7", ARRAY_SIZE(pwm7), pwm7 }, ++ { "PWM8G1", ARRAY_SIZE(pwm8g1), pwm8g1 }, ++ { "PWM9G1", ARRAY_SIZE(pwm9g1), pwm9g1 }, ++ { "PWM10G1", ARRAY_SIZE(pwm10g1), pwm10g1 }, ++ { "PWM11G1", ARRAY_SIZE(pwm11g1), pwm11g1 }, ++ { "PWM12G1", ARRAY_SIZE(pwm12g1), pwm12g1 }, ++ { "PWM13G1", ARRAY_SIZE(pwm13g1), pwm13g1 }, ++ { "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 }, ++ { "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 }, ++ { "PWM8G0", ARRAY_SIZE(pwm8g0), pwm8g0 }, ++ { "PWM9G0", ARRAY_SIZE(pwm9g0), pwm9g0 }, ++ { "PWM10G0", ARRAY_SIZE(pwm10g0), pwm10g0 }, ++ { "PWM11G0", ARRAY_SIZE(pwm11g0), pwm11g0 }, ++ { "PWM12G0", ARRAY_SIZE(pwm12g0), pwm12g0 }, ++ { "PWM13G0", ARRAY_SIZE(pwm13g0), pwm13g0 }, ++ { "PWM14G0", ARRAY_SIZE(pwm14g0), pwm14g0 }, ++ { "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 }, + }; + + static int ast2600_pinctrl_get_groups_count(struct udevice *dev) +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 2984b7976637..95e82ee5ddf6 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -50,3 +50,11 @@ config PWM_SUNXI + help + This PWM is found on H3, A64 and other Allwinner SoCs. It supports a + programmable period and duty cycle. A 16-bit counter is used. ++ ++config PWM_ASPEED ++ bool "Enable support for the Aspeed AST2600 PWM" ++ depends on DM_PWM ++ depends on ASPEED_AST2600 ++ help ++ This PWM is found on Aspeed AST2600 SoC. It supports a programmable ++ period and duty cycle. A 16-bit counter is used. +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index a837c35ed2e3..770b054c3f3b 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -16,3 +16,4 @@ obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o + obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o + obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o + obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o ++obj-$(CONFIG_PWM_ASPEED) += aspeed_pwm.o +diff --git a/drivers/pwm/aspeed_pwm.c b/drivers/pwm/aspeed_pwm.c +new file mode 100644 +index 000000000000..111e2971d226 +--- /dev/null ++++ b/drivers/pwm/aspeed_pwm.c +@@ -0,0 +1,172 @@ ++// SPDX-License-Identifier: GPL ++// Copyright (c) 2021 Intel Corporation ++ ++#include <asm/io.h> ++#include <linux/bitfield.h> ++#include <clk.h> ++#include <common.h> ++#include <dm.h> ++#include <linux/ioport.h> ++#include <pwm.h> ++#include <reset.h> ++#include <asm/arch/scu_ast2600.h> ++ ++#define NSEC_PER_SEC 1000000000L ++ ++#define ASPEED_PWM_CTRL 0x00 /* PWM0 General Register */ ++#define ASPEED_PWM_CTRL_CH(x) (((x) * 0x10) + ASPEED_PWM_CTRL) ++#define PWM_LOAD_AS_WDT BIT(19) ++#define PWM_DUTY_LOAD_AS_WDT_EN BIT(18) ++#define PWM_DUTY_SYNC_DIS BIT(17) ++#define PWM_CLK_ENABLE BIT(16) ++#define PWM_LEVEL_OUTPUT BIT(15) ++#define PWM_INVERSE BIT(14) ++#define PWM_OPEN_DRAIN_EN BIT(13) ++#define PWM_PIN_EN BIT(12) ++#define PWM_CLK_DIV_H_MASK GENMASK(11, 8) ++#define PWM_CLK_DIV_L_MASK GENMASK(7, 0) ++ ++#define ASPEED_PWM_DUTY_CYCLE 0x04 /* PWM0 Duty Cycle Register */ ++#define ASPEED_PWM_DUTY_CYCLE_CH(x) (((x) * 0x10) + ASPEED_PWM_DUTY_CYCLE) ++#define PWM_PERIOD_MASK GENMASK(31, 24) ++#define PWM_RISING_FALLING_AS_WDT_MASK GENMASK(23, 16) ++#define PWM_RISING_POINT_MASK GENMASK(15, 8) ++#define PWM_FALLING_POINT_MASK GENMASK(7, 0) ++ ++#define PWM_PERIOD_MAX 255 ++ ++struct aspeed_pwm_priv { ++ void __iomem *base; ++ ulong clk_freq; ++ u32 clk_tick_ns; ++}; ++ ++static int aspeed_pwm_set_config(struct udevice *dev, uint channel, ++ uint period_ns, uint duty_ns) ++{ ++ struct aspeed_pwm_priv *priv = dev_get_priv(dev); ++ u8 div_h, div_l, period_value, falling_point, rising_point; ++ u32 ctrl_value, duty_value, tick_ns; ++ ++ /* ++ * We currently avoid using 64bit arithmetic by using the ++ * fact that anything faster than 1Hz is easily representable ++ * by 32bits. ++ */ ++ if (period_ns > NSEC_PER_SEC) ++ return -ERANGE; ++ ++ for (div_l = 0; div_l <= 0xff; div_l++) { ++ for (div_h = 0; div_h <= 0xf; div_h++) { ++ tick_ns = priv->clk_tick_ns * BIT(div_h) * (div_l + 1); ++ if (tick_ns * PWM_PERIOD_MAX >= period_ns) ++ break; ++ } ++ if (tick_ns * PWM_PERIOD_MAX >= period_ns) ++ break; ++ } ++ ++ if (period_ns / tick_ns > PWM_PERIOD_MAX) ++ return -ERANGE; ++ ++ ctrl_value = FIELD_PREP(PWM_CLK_DIV_H_MASK, div_h) | ++ FIELD_PREP(PWM_CLK_DIV_L_MASK, div_l); ++ period_value = period_ns / tick_ns; ++ falling_point = 0; ++ rising_point = duty_ns / tick_ns; ++ duty_value = FIELD_PREP(PWM_PERIOD_MASK, period_value) | ++ FIELD_PREP(PWM_RISING_POINT_MASK, rising_point) | ++ FIELD_PREP(PWM_FALLING_POINT_MASK, falling_point); ++ ++ clrsetbits_le32(priv->base + ASPEED_PWM_DUTY_CYCLE_CH(channel), ++ PWM_PERIOD_MASK | PWM_RISING_POINT_MASK | ++ PWM_FALLING_POINT_MASK, duty_value); ++ clrsetbits_le32(priv->base + ASPEED_PWM_CTRL_CH(channel), ++ PWM_CLK_DIV_H_MASK | PWM_CLK_DIV_L_MASK, ctrl_value); ++ ++ return 0; ++} ++ ++static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable) ++{ ++ struct aspeed_pwm_priv *priv = dev_get_priv(dev); ++ ++ debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel); ++ ++ clrsetbits_le32(priv->base + ASPEED_PWM_CTRL_CH(channel), ++ PWM_CLK_ENABLE | PWM_PIN_EN, ++ enable ? PWM_CLK_ENABLE | PWM_PIN_EN : 0); ++ ++ return 0; ++} ++ ++static int aspeed_pwm_ofdata_to_platdata(struct udevice *dev) ++{ ++ struct aspeed_pwm_priv *priv = dev_get_priv(dev); ++ struct resource res_regs; ++ int ret; ++ ++ ret = dev_read_resource(dev, 0, &res_regs); ++ if (ret < 0) ++ return ret; ++ ++ priv->base = (void __iomem *)res_regs.start; ++ ++ return 0; ++} ++ ++static int aspeed_pwm_probe(struct udevice *dev) ++{ ++ struct aspeed_pwm_priv *priv = dev_get_priv(dev); ++ struct reset_ctl reset_ctl; ++ struct clk hclk; ++ int ret; ++ ++ ret = clk_get_by_index(dev, 0, &hclk); ++ if (ret) { ++ pr_err("%s: could not get clock: %d\n", dev->name, ret); ++ return ret; ++ } ++ ++ priv->clk_freq = clk_get_rate(&hclk); ++ priv->clk_tick_ns = NSEC_PER_SEC / priv->clk_freq; ++ (void) clk_free(&hclk); ++ ++ ret = reset_get_by_index(dev, 0, &reset_ctl); ++ if (ret) { ++ pr_err("%s: Failed to get reset signal: %d\n", dev->name, ret); ++ return ret; ++ } ++ ++ ret = reset_assert(&reset_ctl); ++ if (!ret) { ++ mdelay(10); ++ ret = reset_deassert(&reset_ctl); ++ } ++ ++ return ret; ++} ++ ++static const struct pwm_ops aspeed_pwm_ops = { ++ .set_config = aspeed_pwm_set_config, ++ .set_enable = aspeed_pwm_set_enable, ++}; ++ ++static const struct udevice_id aspeed_pwm_ids[] = { ++ { .compatible = "aspeed,ast2600-pwm" }, ++ { } ++}; ++ ++U_BOOT_DRIVER(aspeed_pwm) = { ++ .name = "aspeed_pwm", ++ .id = UCLASS_PWM, ++ .of_match = aspeed_pwm_ids, ++ .ops = &aspeed_pwm_ops, ++ .ofdata_to_platdata = aspeed_pwm_ofdata_to_platdata, ++ .priv_auto_alloc_size = sizeof(struct aspeed_pwm_priv), ++ .probe = aspeed_pwm_probe, ++}; ++ ++MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Aspeed AST2600 PWM Driver"); +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0031-Add-a-workaround-to-fix-AST2600-A0-booting-issue.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0031-Add-a-workaround-to-fix-AST2600-A0-booting-issue.patch new file mode 100644 index 000000000..9444dde99 --- /dev/null +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0031-Add-a-workaround-to-fix-AST2600-A0-booting-issue.patch @@ -0,0 +1,32 @@ +From 58ed1cb4ac3229b484c983a2e4982fad13da0e06 Mon Sep 17 00:00:00 2001 +From: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +Date: Fri, 21 May 2021 17:24:13 -0700 +Subject: [PATCH] Add a workaround to fix AST2600 A0 booting issue + +AST2600 A0 doesn't boot with 88KB SRAM setting so this commit adds +a workaround which pins SRAM size to 64KB to make A0 able to boot. + +Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com> +--- + arch/arm/include/asm/arch-aspeed/platform.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h +index f016bdaba3e7..192e3b977a34 100644 +--- a/arch/arm/include/asm/arch-aspeed/platform.h ++++ b/arch/arm/include/asm/arch-aspeed/platform.h +@@ -53,7 +53,11 @@ + #define ASPEED_MAC_COUNT 4 + #define ASPEED_DRAM_BASE 0x80000000 + #define ASPEED_SRAM_BASE 0x10000000 ++#if 1 /* AST2600 A0 doesn't boot with 88K setting so pin SRAM size to 64K */ ++#define ASPEED_SRAM_SIZE 0x10000 ++#else + #define ASPEED_SRAM_SIZE 0x16000 ++#endif + #define ASPEED_FMC_CS0_BASE 0x20000000 + #else + #err "No define for platform.h" +-- +2.17.1 + diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg index 1ac02608b..e61f3de1e 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg @@ -12,6 +12,8 @@ CONFIG_CMD_IRQ=y CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x2400000 CONFIG_BOARD_LATE_INIT=y +CONFIG_DM_PWM=y +CONFIG_PWM_ASPEED=y CONFIG_TARGET_EVB_AST2600A1=n CONFIG_PHY_NCSI=n CONFIG_CMD_USB=n diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend index 29d938c6e..dd03c1f17 100644 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend @@ -7,7 +7,7 @@ FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:" SRC_URI_append_intel-ast2600 = " \ file://intel.cfg \ file://0001-Add-ast2600-intel-as-a-new-board.patch \ - file://0021-AST2600-Enable-host-searial-port-clock-configuration.patch \ + file://0002-AST2600-Enable-host-searial-port-clock-configuration.patch \ file://0003-ast2600-intel-layout-environment-addr.patch \ file://0004-AST2600-Adjust-default-GPIO-settings.patch \ file://0005-Ast2600-Enable-interrupt-in-u-boot.patch \ @@ -30,10 +30,12 @@ SRC_URI_append_intel-ast2600 = " \ file://0023-Add-WDT-to-u-boot-to-cover-booting-failures.patch \ file://0024-fix-SUS_WARN-handling-logic.patch \ file://0025-ast2600-PFR-platform-EXTRST-reset-mask-selection.patch \ - file://0025-Enable-PCIe-L1-support.patch \ + file://0026-Enable-PCIe-L1-support.patch \ file://0027-ast2600-Add-Mailbox-init-function.patch \ file://0028-Improve-randomness-of-mac-address-generation.patch \ file://0029-Set-UART-routing-in-lowlevel_init.patch \ + file://0030-Add-Aspeed-PWM-uclass-driver.patch \ + file://0031-Add-a-workaround-to-fix-AST2600-A0-booting-issue.patch \ " # CVE-2020-10648 vulnerability fix @@ -57,12 +59,6 @@ SRC_URI_append_intel-ast2600 = " \ file://0001-lib-uuid-Fix-unseeded-PRNG-on-RANDOM_UUID-y.patch \ " -# CVE-2019-13104 vulnerability fix -FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files/CVE-2019-13104:" -SRC_URI_append_intel-ast2600 = " \ - file://0001-CVE-2019-13104-ext4-check-for-underflow-in-ext4fs_re.patch \ - " - # CVE-2019-13105 vulnerability fix FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files/CVE-2019-13105:" SRC_URI_append_intel-ast2600 = " \ @@ -70,6 +66,12 @@ SRC_URI_append_intel-ast2600 = " \ file://0002-CVE-2019-13105-ext4-fix-double-free-in-ext4_cache_re.patch \ " +# CVE-2019-13104 vulnerability fix +FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files/CVE-2019-13104:" +SRC_URI_append_intel-ast2600 = " \ + file://0001-CVE-2019-13104-ext4-check-for-underflow-in-ext4fs_re.patch \ + " + # CVE-2019-13106 vulnerability fix FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files/CVE-2019-13106:" SRC_URI_append_intel-ast2600 = " \ @@ -95,5 +97,7 @@ PFR_SRC_URI = " \ SRC_URI_append_intel-ast2600 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" do_install_append () { + install -m 0644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config } +RDEPENDS_${PN} = "udev-aspeed-mtd-partitions" diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend index 2e230c2a2..c73fd75cc 100644..120000 --- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend +++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-fw-utils-aspeed-sdk_%.bbappend @@ -1,18 +1 @@ -COMPATIBLE_MACHINE = "intel-ast2600" -FILESEXTRAPATHS_append_intel-ast2600:= "${THISDIR}/files:" - -SRC_URI_append_intel-ast2600 = " \ - file://intel.cfg \ - file://0001-Add-ast2600-intel-as-a-new-board.patch \ - file://0003-ast2600-intel-layout-environment-addr.patch \ - " -PFR_SRC_URI = " \ - file://0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch \ - " -SRC_URI_append_intel-ast2600 += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', PFR_SRC_URI, '', d)}" - -do_install_append () { - install -m 0644 ${WORKDIR}/fw_env.config ${D}${sysconfdir}/fw_env.config - install -m 0644 ${WORKDIR}/fw_env.config ${S}/tools/env/fw_env.config -} -RDEPENDS_${PN} = "udev-aspeed-mtd-partitions" +u-boot-aspeed-sdk_%.bbappend
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