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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
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2024-04-27drm/amd/display: Add misc DC changes for DCN401Aurabindo Pillai1-28/+16
Add miscellaneous changes to enable DCN401 init Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-27drm/amd/display: Add some DCN401 reg name to macro definitionsAurabindo Pillai1-0/+11
Update macros to cover DCN 4.0.1. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-04-10drm/amd/display: handle invalid connector indicesJoshua Aberback1-1/+1
[Why] The function to count the number of valid connectors does not guarantee that the first n indices are valid, only that there exist n valid indices. When invalid indices are present, this results in later valid connectors being missed, as processing would end after checking n indices. [How] - count valid indices separately from total indices examined - add explicit definition of MAX_LINKS Reviewed-by: Dillon Varone <dillon.varone@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-23drm/amd/display: add power_state and pme_pending flagMuhammad Ahmed1-0/+1
[what] Adding power_state to dc.h and pme_pending flag to clk_mgr_internal.h Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-16drm/amd/display: Floor to mhz when requesting dpp disp clock changes to SMUWenjing Liu1-0/+5
[Why] SMU uses discrete dpp and disp clock levels. When we submit SMU request for clock changes in Mhz we need to floor the requested value from Khz so SMU will choose the next higher clock level in Khz to set. If we ceil to Mhz, SMU will have to choose the next higher clock level after the ceil, which could result in unnecessarily jumpping to the next level. For example, we request 1911,111Khz which is exactly one of the SMU preset level. If we pass 1912Mhz, SMU will choose 2150,000 khz. If we pass 1911Mhz, SMU will choose 1911,111kHz, which is the expected value. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-09-27drm/amd/display: switch DC over to the new DRM logging macrosHamza Mahfooz1-1/+1
For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-09-12drm/amd/display: fix some non-initialized register mask and settingCharlene Liu1-1/+15
[why] fix some non-initialized register mask and update golden setting Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-28drm/amd/display: fill in clock values when DPM is not enabledSamson Tam1-0/+2
[Why] For individual feature testing, PMFW may not report all clock values back. Driver will default them to 0 but this will cause the BB table to be skipped and default to one state with max clocks. [How] Add helper function to scan through initial clock values and populate them with default clock limits so that BB table can be built. Add dpm_enabled flag to check when DPM is not enabled and to trigger helper function. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by: Samson Tam <samson.tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-03drm/amd/display: add CLKMGR changes for DCN32/321Aurabindo Pillai1-2/+43
Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-10-04drm/amd/display: add cyan_skillfish display supportZhan Liu1-0/+13
[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Jun Lei <jun.lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08drm/amd/display: Round KHz up when calculating clock requestsAric Cyr1-0/+5
[Why] When requesting clocks from SMU which takes MHz inputs, DC will round down KHz when converting to MHz, thus potentially requesting too low a clock value. [How] Round up (ceil) when converting KHz to MHz for clock requests to SMU. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-09drm/amd/display: Simplify bool comparisonJiapeng Chong1-2/+2
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h:319:11-23: WARNING: Comparison to bool. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-05drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher1-6/+1
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-08-05drm/amd/display: Fix logger contextHarry Wentland1-1/+2
[Why&How] use correct logger context Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-27drm/amd/display: dce60_timing_generator: add DCE6 specific functions (v2)Mauro Rossi1-0/+11
[Why] DCE6 has CRTC_PREFETCH_EN bit in CRTC_CONTROL register DCE6 has no CRTC_LEGACY_REQUESTOR_EN bit in CRTC_START_LINE_CONTROL register DCE6 has no CRTC_CRC_CNTL register [How] Modify dce60_timing_generator_enable_advanced_request() function Add dce60_configure_crc() function and dce60_is_tg_enabled() kept as static Use dce60_configure_crc() function in dce60_tg_funcs v2: remove unused variable (Alex) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-14drm/amd/display: reduce sr_xxx_time by 3 us when ppt disableChiawen Huang1-0/+1
[Why] when ppt disabled, the watermark doesn't get fine tune causing underflow. [How] It is a temporary solution to reduce sr_xxx_time by 3 us when ppt disable. Signed-off-by: Chiawen Huang <chiawen.huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-08drm/amd/display: Request PHYCLK adjustment on PHY enable/disableJoshua Aberback1-0/+2
[Why] Currently we don't explicitly send a request for a minimum PHYCLK, and we hope that the dependencies other clocks have will raise PHYCLK when needed. [How] - new clk_mgr function to keep track of PHYCLK requirements - request maximum requirement across all links - remove PHYCLK from clock state comparator, as it doesn't come from DML Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-02drm/amd/display: Preserve gpu memory allocation for life of dcJoshua Aberback1-0/+2
[Why] We want to keep the same buffer allocated for use during multiple hardware initializations. [How] - allocate gpu memory buffer on clock manager construct - free gpu memory buffer on clock manager destruct Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Add DCN3 CLK_MGRBhawanpreet Lakha1-0/+14
Adds support for handling of clocking relevant to the DCN3 block Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-25drm/amd/display: do not force UCLK DPM to stay at highest state during ↵Samson Tam1-0/+4
display off in DCN2 [Why] Add optimization to allow pstate change support when all displays are off in DCN2. [How] Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all valid stream_status[]. If plane_count is 0, then there are no active or virtual streams present. Use plane_count == 0 as extra condition to enable p_state_change_support in dcn2_update_clocks(). Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-11-13drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTEDBhawanpreet Lakha1-12/+0
[Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-25drm/amd/display: move dispclk vco freq to clk mgr baseDmytro Laktyushkin1-2/+0
This value will be needed by dml and therefore should be externally accessible. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-11drm/amd/display: use vbios message to call smu for dpm levelCharlene Liu1-0/+15
[Description] use vbios message to call smu for dpm level also only program dmdata in vsyncflip as HW requirement. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-11drm/amd/display: Restore should_update_pstate_support after bad revertJoshua Aberback1-2/+8
[Why] This function was mistakenly reverted as part of a legitimate revert. The old version that was reverted to has bad logic, and is causing situations where p-state change support is being toggled when it shouldn't be, resulting in hangs. Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-03drm/amd/display: Revert fixup DPP programming sequenceWesley Chalmers1-8/+2
[WHY] This change was made because DTO programming was double-buffered, which is itself an issue. After deactivating the DTO double buffer, this change becomes unnecessary. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: fixup DPP programming sequenceJun Lei1-2/+8
[why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Add DFS reference clock fieldYongqiang Sun1-0/+2
Add to clk_mgr_internal struct, for future use. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Add SMU version field to clk_mgr_internalFatemeh Darbehani1-0/+1
For some platforms, we need to know SMU version for driver/SMU compatibility. This change adds that field. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: move bw calc code into helpersEric Yang1-0/+2
[Why] For better readability and reusability [How] Move snippets of BW calculation code into helpers. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Fatemeh Darbehani <Fatemeh.Darbehani@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: update DCN2 uclk switch timeJun Lei1-0/+6
[why] value commited to by HW team is going to be higher than pre-silicon, and will cause underflow if driver not updated [how] update hardcoded value, update pstate switching logic to fix case where with long uclk time we won't allow switch even when we should Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Add DCN2 clk mgrHarry Wentland1-5/+77
Adds support for handling of clocking relevant to the DCN2 block, including programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31drm/amd/display: Refactor clk_mgr functionsEric Yang1-0/+4
[Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] * Pull get_active_display_cnt out to clk_mgr. * Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31drm/amd/display: Move CLK_BASE_INNER macroEric Yang1-2/+1
This macro is specificly used by RV1. Move it to the appropriate location. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-05-31drm/amd/display: make clk mgr soc specificEric Yang1-0/+208
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-08 11:53:43 +0300