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path: root/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
AgeCommit message (Expand)AuthorFilesLines
2020-12-23drm/amdgpu: drop psp ih programming for sriov guest on naviHawking Zhang1-16/+2
2020-12-23drm/amdgpu: de-initialize software ih ringHawking Zhang1-0/+1
2020-12-23drm/amdgpu: set ih soft ring enabled flag for vega and naviHawking Zhang1-0/+3
2020-12-23drm/amdgpu: retire the vega20 code path from navi10 ih blockHawking Zhang1-38/+2
2020-12-23drm/amdgpu: switch to common decode iv helperHawking Zhang1-46/+1
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for navi10Hawking Zhang1-38/+14
2020-12-23drm/amdgpu: switch to ih_enable_ring for navi10Hawking Zhang1-90/+12
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for navi10Hawking Zhang1-133/+33
2020-12-23drm/amdgpu: switch to ih_init_register_offset for navi10Hawking Zhang1-0/+3
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for navi10Hawking Zhang1-0/+45
2020-12-23drm/amdgpu: add helper to enable an ih ring for navi10Hawking Zhang1-0/+52
2020-12-23drm/amdgpu: add helper to init ih ring regs for navi10Hawking Zhang1-0/+47
2020-12-02drm/amd/amdgpu/navi10_ih: Add descriptions for 'ih' and 'entry'Lee Jones1-0/+5
2020-11-24drm/amdgpu: enabled software IH ring for NaviChristian König1-0/+7
2020-10-12drm/amdgpu: add ih ip block for dimgrey_cavefishTao Zhou1-0/+1
2020-10-05drm/amdgpu: use gpu virtual address for interrupt packet write space for vangoghHuang Rui1-2/+5
2020-10-05drm/amdgpu: add van gogh support for ih blockHuang Rui1-0/+1
2020-09-03drm/amdgpu: enable ih1 ih2 for Arcturus onlyAlex Sierra1-11/+19
2020-07-21drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)Chengming Gui1-0/+45
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen1-0/+1
2020-06-03drm/amdgpu: add ih ip block for sienna_cichlidLikun Gao1-4/+17
2020-04-04amdgpu/drm: remove psp access on navi10 for sriovAlex Sierra1-9/+9
2020-04-01drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5Alex Sierra1-0/+19
2020-04-01drm/amdgpu: call psp to program ih cntl in SR-IOV for NaviAlex Sierra1-10/+80
2020-04-01drm/amdgpu: enable IH ring 1 and ring 2 for naviAlex Sierra1-16/+189
2020-03-05drm/amdgpu: Rearm IRQ in Navi10 SR-IOV if IRQ lostSamir Dhume1-0/+36
2020-01-23drm/amdgpu: remove unnecessary conversion to boolNirmoy Das1-1/+1
2019-12-23drm/amdgpu: Remove unneeded variable 'ret' in navi10_ih.cMa Feng1-2/+1
2019-09-14drm/amdgpu: switch to new amdgpu_nbio structureHawking Zhang1-2/+2
2019-07-31drm/amdgpu: drop drmP.h from navi10_ih.cAlex Deucher1-1/+2
2019-06-21drm/amdgpu: add navi10 ih ip block (v3)Hawking Zhang1-0/+486
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-19 17:14:15 +0300