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path: root/arch/x86/cpu/ivybridge/bd82x6x.c
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2021-02-02common: Drop asm/global_data.h from common headerSimon Glass1-0/+1
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2020-05-19common: Drop linux/bitops.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop linux/delay.h from common headerSimon Glass1-0/+1
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-19common: Drop log.h from common headerSimon Glass1-0/+1
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass1-0/+15
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20x86: ivybridge: Add a way to get the HDA config settingSimon Glass1-2/+25
Add a way check to whether HD audio is enabled. Use ioctl() to avoid adding too many unusual operations to PCH. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini1-2/+1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2017-02-06x86: ivybridge: Declare global data where it is usedSimon Glass1-0/+2
Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11dm: x86: Move link to use driver model for videoSimon Glass1-12/+0
Update the configuration to use the new driver. Drop the existing plumbing code and unused header files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-17dm: Rename disk uclass to ahciSimon Glass1-1/+1
This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17x86: Move common LPC code to its own placeSimon Glass1-14/+2
Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17x86: Add the root-complex block to common intel registersSimon Glass1-0/+1
This is similar to MCH in that it is used in various drivers. Add it to the common header. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-21x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng1-0/+4
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-05x86: pch: Implement get_gpio_base opBin Meng1-0/+33
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Rename get_sbase op to get_spi_baseBin Meng1-2/+2
Spell out 'sbase' to 'spi_base' so that it looks clearer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05dm: pch: Remove pch_get_version opBin Meng1-6/+0
pch_get_version op was only used by the ich spi controller driver, and does not really provide a good identification of pch controller so far, since we see plenty of Intel PCH chipsets and one differs from another a lot, which is not simply either a PCHV_7 or PCHV_9. Now that ich spi controller driver was updated to not get such info from pch, the pch_get_version op is useless now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-01-24x86: ivybridge: Use syscon for the GMA deviceSimon Glass1-9/+5
Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Drop special EHCI initSimon Glass1-3/+0
This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move code from pch.c to bd82x6x.cSimon Glass1-0/+129
This code relates to the PCH, so we should move it into the same file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass1-4/+0
Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move lpc_enable() into gma.cSimon Glass1-1/+0
This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Use the SATA driver to do the initSimon Glass1-8/+5
Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass1-16/+0
This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Do the SATA init before relocationSimon Glass1-2/+0
The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move northbridge and PCH init into driversSimon Glass1-42/+0
Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Move CPU init code into the driverSimon Glass1-6/+0
Use the CPU driver's probe() method to perform the CPU init. This will happen automatically when the first CPU is probed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Rename lpc_init() to lpc_init_extra()Simon Glass1-1/+1
In preparation for adding an init() method to the LPC uclass, rename this existing function so that it will not conflict. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Rename bd82x6x_init()Simon Glass1-1/+1
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove this in a later patch. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24x86: ivybridge: Set up the LPC device using driver modelSimon Glass1-0/+3
Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass1-1/+46
At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12dm: x86: ivybridge: Convert graphics init to use DM PCI APISimon Glass1-2/+4
Use the driver-model PCI functions here where possible. For now we have to search for the device with pci_bus_find_bdf() but at some point we can put this in a proper driver and avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-21x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng1-32/+0
Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18dm: x86: Add a uclass for a Platform Controller HubSimon Glass1-9/+0
Add a simple uclass for this chip which is often found in x86 systems where the CPU is a separate device. The device can have children, so make it scan the device tree for these. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18dm: x86: pci: Convert chromebook_link to use driver model for pciSimon Glass1-1/+23
Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-17x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass1-16/+16
These functions currently use a generic name, but they are for x86 only. This may introduce confusion and prevents U-Boot from using these names more widely. In fact it should be possible to remove these at some point and use generic functions, but for now, rename them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25x86: Add initial video device init for Intel GMASimon Glass1-1/+12
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add northbridge init functionsSimon Glass1-0/+2
Add init for the northbridge, another part of the platform controller hub. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: Add init for model 206AX CPUSimon Glass1-0/+6
Add the setup code for the CPU so that it can be used at full speed. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Set up EHCI USBSimon Glass1-0/+2
Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add SATA initSimon Glass1-0/+20
Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add additional LPC initSimon Glass1-0/+6
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25x86: ivybridge: Add support for BD82x6x PCHSimon Glass1-0/+99
Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-20 15:57:27 +0300