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2024-04-29dts: Add amp dts node.Minda Chen3-2/+121
Add different domain in dts node for sbi boot and disable gmac1 node. make DEVICE_TREE=starfive_jh7110-amp to build uboot amp image. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-04-26spl: amp: Enable UART2 and move rtos image to memoryMinda Chen1-0/+3
Enable UART2 for rtos and move rtos image to running memory. The image size is 832KB. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2024-02-23Merge branch 'CR_9208_DEVKITS_EEPROM_ziv.xu' into 'jh7110-master'andy.hu1-2/+2
CR_9208_DEVKITS_EEPROM_ziv.xu See merge request sdk/u-boot!79
2024-02-18riscv: dts: change eeprom model for devkitsZiv Xu1-2/+2
change eeprom model for devkits Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
2024-02-06riscv: dts: change eeprom model for visionfiveZiv Xu1-2/+2
change eeprom model for visionfive Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
2023-12-05riscv: dts: jh7110: Change the node name "i2c@12050000" to "i2c5@12050000"Hal Feng1-1/+1
So the I2C adapter can be recognized in OpenSBI. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: dts: Change compatible "raydium,rm68200" to "starfive,seeed"Hal Feng2-2/+2
As drivers/video/raydium-rm68200-starfive.c is renamed to drivers/video/starfive_seeed_panel.c, change the dts accordingly. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: dts: Add StarFive JH7110 Devkits board device treeHal Feng3-0/+401
Add device tree for StarFive JH7110 Devkits board. The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: dts: jh7110: Sync with Devkits repoHal Feng2-13/+47
To be compatible with the Devkits board. The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29board: starfive: Add TARGET_STARFIVE_DEVKITS to KconfigHal Feng1-0/+4
Add board support for StarFive Devkits. The code is ported from tag JH7110_DVK_515_v3.9.3 of Devkits repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: dts: Add StarFive VisionFive 2 board device treeHal Feng4-113/+493
Add device tree for StarFive VisionFive 2 board. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: dts: jh7110: Add a new clock input to gmacHal Feng1-4/+8
To be compatible with the VisionFive 2 board. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29board: starfive: Add TARGET_STARFIVE_VISIONFIVE2 to KconfigHal Feng1-3/+3
Add board support for StarFive VisionFive 2. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-11-29riscv: cpu: jh7110: Add EEPROM supportHal Feng1-0/+14
Add a header to easily use the EEPROM interface. The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-09-11riscv: dts: Add link state register to PCIe syscon nodes.Kevin.xie1-2/+2
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2023-09-05dts: usb: Add starfive,usb2-only to zeroMinda Chen1-0/+1
Add starfive,usb2-only to zero in evb board. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-25dts: usb: Add USB 3.0 clock dts.Minda Chen1-0/+15
Add evb USB 3.0 clock dts. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-08-25dts: starfive: devkits: Update usb device tree nodeYanhong Wang1-4/+8
Updated USB Device Tree Node to support USB Device functionality and is consistent with Kernel. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-07-28riscv: dts: starfive: limit cclk_in frequencyWilliam Qiu1-0/+2
The frequency of cclk_in is limited to 50M, so that it does not do internal part frequency and goes by-pass mode. And delete syscon node. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
2023-07-26gpio: starfive: Add SET_DS/SET_PULL/SET_SLEW supportSamin Guo1-1/+23
SET_DS/SET_PULL/SET_SLEW can configure the properties of the GPIO Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-20board: starfive: evb: use dram_init in splSamin Guo2-1/+7
dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not need it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-20Merge branch 'CR_6604_1G_DDR_SYNC_samin.guo' into 'jh7110-master'andy.hu1-40/+10
CR6604：dram: jh7110: sync from devkits/vf2 See merge request sdk/u-boot!59
2023-07-18riscv: dts: starfive: jh7110: replace mipi&hdmi nodeKeith Zhao1-4/+4
replace mipi&hdmi node , hdmi logo will start begin mipi Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
2023-07-18dram: jh7110: remove resize-ddr functionSamin Guo1-40/+10
The resize-ddr should be board-level code Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: starfive: jh7110: Add 1G supportSamin Guo1-0/+1
add 1G DDR tuning cfg Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Add CONFIG_ID_EEPROM to determine if EEPROM is availableSamin Guo1-18/+26
When eeprom reads, you need to determine whether eeprom supports it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-07-10dram: jh7110: Macro definitions STARFIVE_JH7110_EEPROM_DDRINFO_OFFSETSamin Guo1-1/+2
In order to read DDR info from eeprom. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-06-25dram: jh7110: Add resize DDR info from EEPROM.Samin Guo1-2/+47
sync from vf2 and add resize DDR info from EEPROM Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-05-18riscv: dts: starfive: add zicsr_zifencei to riscv,isa stringAndy Hu1-6/+6
Starting from gcc 12.x, csr and fence instructions have been separated from the base I instruction set. special the zicsr_zifencei string to DT riscv,isa string Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
2023-04-23board: starfive: copyright: Standardize the copyright formatYanhong Wang6-6/+6
Unify the content format of the copyright section Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-04-10dts: pmu: remove pmu dts stall cycles config.Minda Chen1-5/+2
class 8 and class9 cpu stall cycles hwcounter is not supported in U74. delete the configuration. Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
2023-04-04riscv: dts: jh7110: Add L2 pretcher configurationSamin Guo1-0/+10
Add L2 pretcher configuration for starfive jh7110 SoC. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2023-03-28riscv: dts: starfive: Add gpio-controller for the gpio nodeHal Feng1-0/+2
Add gpio-controller for node gpio and gpioa. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2023-03-17riscv: support building double-float modulesHeinrich Schuchardt2-3/+27
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-03-17riscv: Fix build against binutils 2.38Alexandre Ghiti1-1/+10
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Christian Stewart <christian@paral.in> Reviewed-by: Rick Chen <rick@andestech.com>
2023-03-08riscv: dts: enable hdmi dts config in ubootkeith.zhao2-46/+13
hdmi can show a bitmap logo while uboot start and the default resolution is 1920x1080@60fps Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2023-02-22riscv: dts: starfive: Enable PCIe host controllerMason Huo2-12/+114
Enable and add pinctrl configuration for PCIe host controller. Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
2023-02-21riscv:uboot:cache driverkeith.zhao1-1/+1
cache driver enabled by config STARFIVE_JH7110_L2CC_FLUSH if not , there is a dump on vf2 Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17dts:riscv:jh7110: add mipi driver nodekeith.zhao2-94/+329
update dts node to support vout mipi driver Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-17riscv:cache:jh7110: add cache driverkeith.zhao3-0/+66
support flush_dcache_range interface STARFIVE_JH7110_L2CC_FLUSH Signed-off-by:keith.zhao<keith.zhao@statfivetech.com>
2023-02-03Merge branch 'CR_3238_Reserved_memory_mason.huo' into 'jh7110-master'andy.hu1-1/+11
CR_3238 exclude opensbi memory range in device tree See merge request sdk/u-boot!27
2023-02-03exclude opensbi memory range in device treeFelix Moessbauer1-1/+11
This patch explicitly excludes the memory range of the OpenSBI in the built-in device tree. When booting EFI, the efi loader has to know about that zone before loading the device tree for Linux, otherwise it tries to access 0x40000000, leading to an access violation. Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
2023-02-02sysreset: provide SBI based sysreset driverHeinrich Schuchardt3-1/+25
Provide sysreset driver using the SBI system reset extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Samuel Holland <samuel@sholland.org>
2023-02-02riscv: add missing SBI extension definitionsHeinrich Schuchardt1-2/+37
Add the System Reset Extension and the Hart State Management Extension definitions. Add missing RFENCE Extension enum values. The SBI 0.1 extension constants are needed for the sbi command. Remove an #ifdef. Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-01-09dts: add boot-hart-id property in dtsminda.chen1-0/+1
boot-hart-id is used by opensbi. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-06Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-master'andy.hu2-0/+20
CR_3049 dts: add i2c5 and attach pmic configuration See merge request sdk/u-boot!22
2023-01-06Merge branch 'CR_2708_VOUTCLK_yanhong.wang' into 'jh7110-master'andy.hu1-1/+0
CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110 See merge request sdk/u-boot!23
2023-01-05clk:starfive: Add vout clock driver for StarFive JH7110Yanhong Wang1-1/+0
Add vout clock driver for StarFive JH7110 Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
2023-01-05dts: add i2c5 and attach pmic configurationminda.chen2-0/+20
i2c5 and pmic is used by opensbi power management ops. Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2023-01-03dts: pmu : add riscv pmu dts configminda.chen1-0/+46
add 7110 performance monitor for perf use Signed-off-by: minda.chen <minda.chen@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-06-02 13:14:15 +0300