Update to internal 0.56

Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>

64 files changed, 2596 insertions, 565 deletions

diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
index ea6aff1d9..bfcec8c9f 100644
--- a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/configuration/entity-manager/WC-Baseboard.json
@@ -2403,7 +2403,7 @@
     ],
     "Name": "WC Baseboard",
     "Probe": [
-        "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': 'WilsonCity'})",
+        "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': 'WilsonCity.*'})",
         "OR",
         "xyz.openbmc_project.FruDevice({'PRODUCT_PRODUCT_NAME': '.*WC'})"
     ],
@@ -2421,4 +2421,4 @@
         "ProductId": 145
     },
     "xyz.openbmc_project.Inventory.Item.System": {}
-}
\ No newline at end of file
+}
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch
new file mode 100644
index 000000000..ea7ca092c
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors/0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch
@@ -0,0 +1,36 @@
+From d06d0a8fabd699fc1cab4fbd6e4572ce0b22a905 Mon Sep 17 00:00:00 2001
+From: James Feist <james.feist@linux.intel.com>
+Date: Thu, 23 Apr 2020 14:01:38 -0700
+Subject: [PATCH 1/1] Only allow drive sensors on bus 2 for ast2500
+
+CPLD doesn't allow multi-master, so readings wont work.
+Put in a work-around to only allow bus 2 transactions.
+
+Tested: Only valid sensors were installed.
+
+Change-Id: Ib9e75ffd0dd64cf548d15cce9a6052332ac5ec43
+Signed-off-by: James Feist <james.feist@linux.intel.com>
+---
+ src/NVMeSensorMain.cpp | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/src/NVMeSensorMain.cpp b/src/NVMeSensorMain.cpp
+index 1858ea9..844f061 100644
+--- a/src/NVMeSensorMain.cpp
++++ b/src/NVMeSensorMain.cpp
+@@ -111,6 +111,12 @@ void createSensors(boost::asio::io_service& io,
+                     rootBus = std::stoi(rootName.substr(0, dash));
+                 }
+ 
++                // HACK: cpld on current products doesn't allow multi-master
++                if (rootBus != 2)
++                {
++                    continue;
++                }
++
+                 std::shared_ptr<NVMeContext> context;
+                 auto findRoot = nvmeDeviceMap.find(rootBus);
+                 if (findRoot != nvmeDeviceMap.end())
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend
new file mode 100644
index 000000000..1c8817772
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2500/recipes-phosphor/sensors/dbus-sensors_%.bbappend
@@ -0,0 +1,3 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI += "file://0001-Only-allow-drive-sensors-on-bus-2-for-ast2500.patch"
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
index 7accd788c..1fbb464b8 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0001-Add-ast2600-intel-as-a-new-board.patch
@@ -1,11 +1,11 @@
-From a40cea99245e624e8fb2e39e26c7e76f1aee67fe Mon Sep 17 00:00:00 2001
+From 2cec5042f3b33c6762073deb9275a66875538d82 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@intel.com>
 Date: Thu, 24 Oct 2019 14:06:33 -0700
 Subject: [PATCH] Add ast2600-intel as a new board
 
 Signed-off-by: Vernon Mauery <vernon.mauery@intel.com>
-Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
  arch/arm/dts/Makefile                  |   3 +-
  arch/arm/dts/ast2600-intel.dts         | 197 ++++++++++++++++
@@ -13,14 +13,15 @@ Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
  arch/arm/mach-aspeed/ast2600/Kconfig   |   8 +
  board/aspeed/ast2600_intel/Kconfig     |  13 ++
  board/aspeed/ast2600_intel/Makefile    |   4 +
- board/aspeed/ast2600_intel/ast-espi.c  | 298 ++++++++++++++++++++++++
+ board/aspeed/ast2600_intel/ast-espi.c  | 292 ++++++++++++++++++++++++
  board/aspeed/ast2600_intel/ast-irq.c   | 399 +++++++++++++++++++++++++++++++++
  board/aspeed/ast2600_intel/ast-irq.h   |   8 +
  board/aspeed/ast2600_intel/ast-timer.c |  59 +++++
- board/aspeed/ast2600_intel/intel.c     | 185 +++++++++++++++
+ board/aspeed/ast2600_intel/intel.c     | 192 ++++++++++++++++
  cmd/Kconfig                            |   2 +-
  common/autoboot.c                      |  10 +
- 13 files changed, 1189 insertions(+), 2 deletions(-)
+ configs/ast2600_openbmc_defconfig      |   2 +-
+ 14 files changed, 1191 insertions(+), 3 deletions(-)
  create mode 100644 arch/arm/dts/ast2600-intel.dts
  create mode 100644 board/aspeed/ast2600_intel/Kconfig
  create mode 100644 board/aspeed/ast2600_intel/Makefile
@@ -338,23 +339,17 @@ index 000000000000..37d2f0064f38
 +obj-y += ast-timer.o
 diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c
 new file mode 100644
-index 000000000000..1852dd3d86e2
+index 000000000000..0fdbf089a450
 --- /dev/null
 +++ b/board/aspeed/ast2600_intel/ast-espi.c
-@@ -0,0 +1,298 @@
-+/*
-+ * Copyright 2018 Intel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ */
+@@ -0,0 +1,292 @@
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2018-2020, Intel Corporation.
 +
 +#include <common.h>
 +#include <asm/io.h>
 +
-+#define AST_LPC_BASE			0x1e6e9000
++#define AST_LPC_BASE			0x1e789000
 +#define AST_ESPI_BASE			0x1e6ee000
 +#define AST_SCU_BASE			0x1e6e2000
 +#define AST_SCU_HW_STRAP2		0x510
@@ -581,7 +576,7 @@ index 000000000000..1852dd3d86e2
 +
 +void espi_init(void)
 +{
-+	if (!readl(AST_SCU_BASE + AST_SCU_HW_STRAP2) &
++	if (~readl(AST_SCU_BASE + AST_SCU_HW_STRAP2) &
 +	    SCU_HW_STRAP_ESPI_ENABLED) {
 +		uint32_t v;
 +
@@ -1126,10 +1121,13 @@ index 000000000000..cf8c69aba5d3
 +}
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
 new file mode 100644
-index 000000000000..03363b80b4f5
+index 000000000000..4a40a050c3da
 --- /dev/null
 +++ b/board/aspeed/ast2600_intel/intel.c
-@@ -0,0 +1,185 @@
+@@ -0,0 +1,192 @@
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2019-2020, Intel Corporation.
++
 +/* Intel customizations of Das U-Boot */
 +#include <common.h>
 +#include <asm/gpio.h>
@@ -1256,15 +1254,12 @@ index 000000000000..03363b80b4f5
 +	       SCU_BASE | SCU_414);
 +}
 +
-+void espi_init(void);
-+int arch_interrupt_init_early(void);
-+
 +static void timer_handler(void *regs)
 +{
 +	printf("+");
 +}
 +
-+void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler);
++extern int arch_interrupt_init_early(void);
 +int board_early_init_f(void)
 +{
 +	/* This is called before relocation; beware! */
@@ -1282,11 +1277,18 @@ index 000000000000..03363b80b4f5
 +	return 0;
 +}
 +
++extern void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler);
 +int board_early_init_r(void)
 +{
 +	debug("board_early_init_r\n");
 +	/* timer_enable(0, 1, timer_handler); */
 +
++	return 0;
++}
++
++extern void espi_init(void);
++int board_late_init(void)
++{
 +	espi_init();
 +
 +	return 0;
@@ -1353,6 +1355,19 @@ index 94133eaeda78..5e69000b848b 100644
  	if (bootdelay >= 0)
  		abort = __abortboot(bootdelay);
  
+diff --git a/configs/ast2600_openbmc_defconfig b/configs/ast2600_openbmc_defconfig
+index 2e2df2e3a235..77c39d848312 100644
+--- a/configs/ast2600_openbmc_defconfig
++++ b/configs/ast2600_openbmc_defconfig
+@@ -13,7 +13,7 @@ CONFIG_FIT=y
+ CONFIG_USE_BOOTARGS=y
+ CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
+ CONFIG_USE_BOOTCOMMAND=y
+-CONFIG_BOOTCOMMAND="bootm 20100000"
++CONFIG_BOOTCOMMAND="bootm 20080000"
+ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+ CONFIG_DISPLAY_BOARDINFO_LATE=y
+ CONFIG_ARCH_EARLY_INIT_R=y
 -- 
 2.7.4
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
index 7868c03d6..1b2cc83a1 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0004-AST2600-Adjust-default-GPIO-settings.patch
@@ -1,4 +1,4 @@
-From 2e848b74af709f84d1e9fe27a58a74bfc686bfff Mon Sep 17 00:00:00 2001
+From b6bce26bf19e74863e145e6e6e1f6e458077a31a Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Fri, 3 Jan 2020 15:14:09 -0800
 Subject: [PATCH] AST2600: Adjust default GPIO settings
@@ -10,14 +10,14 @@ Subject: [PATCH] AST2600: Adjust default GPIO settings
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- board/aspeed/ast2600_intel/intel.c | 44 ++++++++++++++++++++++++++++++++++++++
- 1 file changed, 44 insertions(+)
+ board/aspeed/ast2600_intel/intel.c | 50 ++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
 
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index eb9b3959625e..25c61d1a806c 100644
+index d1ac8651ac6c..b1a08db91bec 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
-@@ -151,6 +151,48 @@ static void sgpio_init(void)
+@@ -162,6 +162,54 @@ static void sgpio_init(void)
  	       SCU_BASE | SCU_414);
  }
  
@@ -50,11 +50,17 @@ index eb9b3959625e..25c61d1a806c 100644
 +#define SCU_610_GPIOB6		BIT(14)
 +	writel(readl(SCU_BASE | SCU_610) | SCU_610_GPIOB6, SCU_BASE | SCU_610);
 +
++	/*
++	 * GPIO C5 has a connection between BMC(3.3v) and CPU(1.0v) so if we
++	 * set it as an logic high output, it will be clipped by a protection
++	 * circuit in the CPU and eventually the signal will be detected as
++	 * logic low. So we leave this GPIO as an input so that the signal
++	 * can be pulled up by a CPU internal resister. The signal will be
++	 * 1.0v logic high resultingy.
++	 */
 +#define GPIO_C5			BIT(21)
-+	writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C5,
++	writel(readl(AST_GPIO_BASE | GPIO_004) & ~GPIO_C5,
 +	       AST_GPIO_BASE | GPIO_004);
-+	writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C5,
-+	       AST_GPIO_BASE | GPIO_000);
 +
 +#define GPIO_G6			BIT(22)
 +	writel(readl(AST_GPIO_BASE | GPIO_024) | GPIO_G6,
@@ -63,10 +69,10 @@ index eb9b3959625e..25c61d1a806c 100644
 +	       AST_GPIO_BASE | GPIO_020);
 +}
 +
- void espi_init(void);
- int arch_interrupt_init_early(void);
- 
-@@ -167,6 +209,8 @@ int board_early_init_f(void)
+ static void timer_handler(void *regs)
+ {
+ 	printf("+");
+@@ -175,6 +223,8 @@ int board_early_init_f(void)
  	 * I am not sure if it actually does anything... */
  	arch_interrupt_init_early();
  
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch
index 66f3d3b12..d5bd4a2b1 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0005-Ast2600-Enable-interrupt-in-u-boot.patch
@@ -1,4 +1,4 @@
-From 143fb89b03af61bd807b0d6f9f11d6801cf8fe69 Mon Sep 17 00:00:00 2001
+From c1561193296d04dd8bd06adca43edac814058367 Mon Sep 17 00:00:00 2001
 From: Kuiying Wang <kuiying.wang@intel.com>
 Date: Fri, 3 Jan 2020 12:52:29 +0800
 Subject: [PATCH] Enable interrupt in u-boot.
@@ -12,27 +12,70 @@ Testedby:
 2. Both ArcherCity and Ast2600 EVB are working well.
 
 Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- arch/arm/lib/vectors.S               |  31 ++++++-
- board/aspeed/ast2600_intel/ast-irq.c | 154 +++++++++++++++++------------------
- 2 files changed, 105 insertions(+), 80 deletions(-)
+ Kconfig                               |  14 +++
+ arch/arm/lib/stack.c                  |   9 ++
+ arch/arm/lib/vectors.S                |  30 +++++-
+ board/aspeed/ast2600_intel/ast-espi.c |   3 +-
+ board/aspeed/ast2600_intel/ast-irq.c  | 185 +++++++++++++++++-----------------
+ board/aspeed/ast2600_intel/ast-irq.h  |   8 --
+ board/aspeed/ast2600_intel/intel.c    |   1 -
+ 7 files changed, 145 insertions(+), 105 deletions(-)
+ delete mode 100644 board/aspeed/ast2600_intel/ast-irq.h
 
+diff --git a/Kconfig b/Kconfig
+index 305b265ed713..a6f68cd13d54 100644
+--- a/Kconfig
++++ b/Kconfig
+@@ -239,6 +239,20 @@ config BUILD_TARGET
+ 	  special image will be automatically built upon calling
+ 	  make / buildman.
+ 
++config USE_IRQ
++	bool "Use interrupts"
++	default n
++
++config STACKSIZE_IRQ
++	depends on USE_IRQ
++	int "Size for IRQ stack (only if USE_IRQ enabled)"
++	default 16384
++
++config STACKSIZE_FIQ
++	depends on USE_IRQ
++	int "Size for FIQ stack (only if USE_IRQ enabled)"
++	default 16384
++
+ endmenu		# General setup
+ 
+ menu "Boot images"
+diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
+index c89a219dd26d..d9a7f49c5623 100644
+--- a/arch/arm/lib/stack.c
++++ b/arch/arm/lib/stack.c
+@@ -24,6 +24,15 @@ int arch_reserve_stacks(void)
+ 	gd->irq_sp = gd->start_addr_sp;
+ 
+ # if !defined(CONFIG_ARM64)
++#  ifdef CONFIG_USE_IRQ
++	gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
++	printf("Reserving %zu Bytes for IRQ stack at: %08lx\n",
++	      CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
++
++	/* 8-byte alignment for ARM ABI compliance */
++	gd->start_addr_sp &= ~0x07;
++#  endif
++
+ 	/* leave 3 words for abort-stack, plus 1 for alignment */
+ 	gd->start_addr_sp -= 16;
+ # endif
 diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
-index 2ca6e2494a7a..e2ed04a204de 100644
+index 2ca6e2494a7a..5a5e60dbdde4 100644
 --- a/arch/arm/lib/vectors.S
 +++ b/arch/arm/lib/vectors.S
-@@ -13,7 +13,7 @@
-  */
- 
- #include <config.h>
--
-+#define CONFIG_USE_IRQ
- /*
-  * A macro to allow insertion of an ARM exception vector either
-  * for the non-boot0 case or by a boot0-header.
-@@ -145,6 +145,17 @@ fiq:
- 
- #else	/* !CONFIG_SPL_BUILD */
+@@ -154,6 +154,17 @@ IRQ_STACK_START_IN:
+ 	.word	0x0badc0de
+ #endif
  
 +#ifdef CONFIG_USE_IRQ
 +/* IRQ stack memory (calculated at run-time) */
@@ -45,15 +88,16 @@ index 2ca6e2494a7a..e2ed04a204de 100644
 +	.word 0x0badc0de
 +#endif
 +
- /* IRQ stack memory (calculated at run-time) + 8 bytes */
- .globl IRQ_STACK_START_IN
- IRQ_STACK_START_IN:
-@@ -277,17 +288,31 @@ not_used:
+ @
+ @ IRQ stack frame.
+ @
+@@ -277,17 +288,30 @@ not_used:
  	bad_save_user_regs
  	bl	do_not_used
  
-+	.align	5
+-
 +#ifdef CONFIG_USE_IRQ
++	.align	5
 +irq:
 +	get_irq_stack
 +	irq_save_user_regs
@@ -66,9 +110,8 @@ index 2ca6e2494a7a..e2ed04a204de 100644
 +	irq_save_user_regs
 +	bl	do_fiq
 +	irq_restore_user_regs
- 
- 	.align	5
 +#else
+ 	.align	5
  irq:
  	get_bad_stack
  	bad_save_user_regs
@@ -82,11 +125,49 @@ index 2ca6e2494a7a..e2ed04a204de 100644
 -
 +#endif /* CONFIG_USE_IRQ */
  #endif	/* CONFIG_SPL_BUILD */
+diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c
+index 0fdbf089a450..1d7ae529612d 100644
+--- a/board/aspeed/ast2600_intel/ast-espi.c
++++ b/board/aspeed/ast2600_intel/ast-espi.c
+@@ -142,7 +142,7 @@ static void espi_handshake_ack(void)
+ 	}
+ }
+ 
+-int espi_irq_handler(struct pt_regs *regs)
++static void espi_irq_handler(void *cookie)
+ {
+ 	uint32_t irq_status = readl(AST_ESPI_BASE + ESPI008);
+ 
+@@ -226,7 +226,6 @@ int espi_irq_handler(struct pt_regs *regs)
+ 		readl(AST_ESPI_BASE + ESPI11C),
+ 		readl(AST_ESPI_BASE + ESPI094),
+ 		readl(AST_ESPI_BASE + ESPI12C), irq_status);
+-	return 0;
+ }
+ 
+ void espi_init(void)
 diff --git a/board/aspeed/ast2600_intel/ast-irq.c b/board/aspeed/ast2600_intel/ast-irq.c
-index f817f8cd7c81..6e91b17ab186 100644
+index f817f8cd7c81..106bb3b4ffb2 100644
 --- a/board/aspeed/ast2600_intel/ast-irq.c
 +++ b/board/aspeed/ast2600_intel/ast-irq.c
-@@ -18,19 +18,6 @@ DECLARE_GLOBAL_DATA_PTR;
+@@ -1,14 +1,7 @@
+-/*
+- * Copyright 2018 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version
+- * 2 of the License, or (at your option) any later version.
+- */
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2018-2020, Intel Corporation.
+ 
+ #include <common.h>
+-#include <netdev.h>
+ #include <asm/io.h>
+ 
+ DECLARE_GLOBAL_DATA_PTR;
+@@ -18,19 +11,6 @@ DECLARE_GLOBAL_DATA_PTR;
  #define GIC_INTERFACE_OFFSET 0x4000
  #define GIC_VIRT_OFFSET 0x6000
  
@@ -106,7 +187,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  /* GIC_DISTRIBUTOR_OFFSET register offsets */
  #define GICD_CTLR 0x000
  #define GICD_TYPER 0x004
-@@ -82,7 +69,9 @@ DECLARE_GLOBAL_DATA_PTR;
+@@ -82,7 +62,9 @@ DECLARE_GLOBAL_DATA_PTR;
  #define GICC_IIDR 0x00fc
  #define GICC_DIR  0x1000
  
@@ -117,7 +198,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  
  /* GIC_INTERFACE_OFFSET register offsets */
  #define GICH_HCR 0x000
-@@ -116,9 +105,10 @@ DECLARE_GLOBAL_DATA_PTR;
+@@ -116,9 +98,10 @@ DECLARE_GLOBAL_DATA_PTR;
  
  #define GIC_VIRT_CPU_IMPLEMENTER_MAGIC 0x0102143b
  
@@ -131,7 +212,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  #define GICD_INT_DEF_PRI_X4 (\
  		(GICD_INT_DEF_PRI << 24) |\
  		(GICD_INT_DEF_PRI << 16) |\
-@@ -129,20 +119,30 @@ DECLARE_GLOBAL_DATA_PTR;
+@@ -129,21 +112,32 @@ DECLARE_GLOBAL_DATA_PTR;
  #define GICD_INT_EN_CLR_X32 0xffffffff
  #define GICD_INT_EN_CLR_PPI 0xffff0000
  #define GICD_INT_EN_SET_SGI 0x0000ffff
@@ -164,9 +245,11 @@ index f817f8cd7c81..6e91b17ab186 100644
 +
 +static size_t max_irq = 0;
  static interrupt_handler_t *handlers[GIC_MAX_IRQ] = {NULL};
++static void *cookies[GIC_MAX_IRQ] = {NULL};
  static unsigned long irq_total = 0;
  static unsigned long irq_counts[GIC_MAX_IRQ] = {0};
-@@ -159,31 +159,40 @@ static inline uint32_t gic_base(void)
+ static uint32_t gbase = 0;
+@@ -159,24 +153,31 @@ static inline uint32_t gic_base(void)
  
  static void enable_gic(void)
  {
@@ -201,8 +284,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  	uint32_t grp = id >> ITLINES_SHIFT;
  	uint32_t grp_bit = 1 << (id & ITLINES_MASK);
  	gicd_writel(grp_bit, GICD_ISENABLERn + grp * sizeof(uint32_t));
-+	gicd_writel(GICD_ITARGET_ALL, GICD_ITARGETSRn + id / 4 * 4);
- }
+@@ -184,6 +185,7 @@ static void enable_irq_id(unsigned int id)
  
  static void disable_irq_id(unsigned int id)
  {
@@ -210,13 +292,13 @@ index f817f8cd7c81..6e91b17ab186 100644
  	uint32_t grp = id >> ITLINES_SHIFT;
  	uint32_t grp_bit = 1 << (id & ITLINES_MASK);
  	gicd_writel(grp_bit, GICD_ICENABLERn + grp * sizeof(uint32_t));
-@@ -193,22 +202,29 @@ static int gic_probe(void)
+@@ -193,34 +195,49 @@ static int gic_probe(void)
  {
  	int i;
  	gbase = gic_base();
+-	enable_gic();
 +	DBG_IRQ("gic_probe GIC base = 0x%x, magicd=0x%x\n",
 +		gbase, gicd_readl(GICD_IIDR));
- 	enable_gic();
  
  	if (gicd_readl(GICD_IIDR) != GIC_DISTRIBUTOR_IMPLEMENTER_MAGIC &&
  	    gicc_readl(GICC_IIDR) != GIC_CPU_IMPLEMENTER_MAGIC &&
@@ -225,24 +307,34 @@ index f817f8cd7c81..6e91b17ab186 100644
 +		printf("error: magic check \n");
  		return 0;
  	}
++
++	disable_gic();
++
  	/* GIC supports up to 1020 lines */
 -	max_irq = ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) << ITLINES_SHIFT;
-+	max_irq = (((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 32) - 1;
++	max_irq = ((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 32;
  	if (max_irq > GIC_MAX_IRQ)
  		max_irq = GIC_MAX_IRQ;
  	/* set all lines to be level triggered N-N */
  	for (i = 32; i < max_irq; i += 16)
 -		gicd_writel(0, GICD_ICFGRn + i / 4);
+-
+-	/* Set priority on all interrupts. */
+-	for (i = 0; i < max_irq; i += 4)
 +		gicd_writel(GICD_ICFG_LEVEL_TRIGGER, GICD_ICFGRn + i / 4);
- 
++
 +	DBG_IRQ("max_irq = 0x%x, typer=0x%x, config=0x%x, maxirq=0x%x\n", max_irq,
 +		(gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1,
 +		gicd_readl(GICD_ICFGRn + 0x8),
 +		((gicd_readl(GICD_TYPER) & ITLINES_MASK) + 1) * 0x20);
- 	/* Set priority on all interrupts. */
- 	for (i = 0; i < max_irq; i += 4)
++	/* Set priority and target on all interrupts. */
++	for (i = 0; i < max_irq; i += 4) {
  		gicd_writel(GICD_INT_DEF_PRI_X4, GICD_IPRIORITYRn + i);
-@@ -218,9 +234,11 @@ static int gic_probe(void)
++		gicd_writel(GICD_ITARGET_ALL, GICD_ITARGETSRn + i);
++	}
+ 
+ 	/* Deactivate and disable all SPIs. */
+ 	for (i = 32; i < max_irq; i += 32) {
  		gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICACTIVERn + i / 8);
  		gicd_writel(GICD_INT_EN_CLR_X32, GICD_ICENABLERn + i / 8);
  	}
@@ -253,10 +345,12 @@ index f817f8cd7c81..6e91b17ab186 100644
  	gicd_writel(GICD_INT_EN_SET_SGI, GICD_ISENABLERn);
 +	/* unmask all priority */
 +	gicc_writel(GICC_UNMASK_ALL_PRIORITY, GICC_PMRn);
++
++	enable_gic();
  
  	return 0;
  }
-@@ -228,6 +246,7 @@ static int gic_probe(void)
+@@ -228,6 +245,7 @@ static int gic_probe(void)
  void irq_free_handler (int irq);
  static void gic_shutdown(void)
  {
@@ -264,7 +358,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  	int i;
  	for (i = 0; i < max_irq; i++)
  	{
-@@ -238,6 +257,7 @@ static void gic_shutdown(void)
+@@ -238,6 +256,7 @@ static void gic_shutdown(void)
  
  int arch_interrupt_init_early(void)
  {
@@ -272,8 +366,11 @@ index f817f8cd7c81..6e91b17ab186 100644
  	return 0;
  }
  
-@@ -249,11 +269,13 @@ int arch_interrupt_init(void)
+@@ -247,28 +266,28 @@ int arch_interrupt_init(void)
+ 	for (i = 0; i < GIC_MAX_IRQ; i++)
+ 	{
  		handlers[i] = NULL;
++		cookies[i] = NULL;
  		irq_counts[i] = 0;
  	}
 +	DBG_IRQ("arch_interrupt_init\n");
@@ -286,13 +383,13 @@ index f817f8cd7c81..6e91b17ab186 100644
  	gic_shutdown();
  	return 0;
  }
-@@ -261,14 +283,12 @@ int arch_interrupt_fini(void)
+ 
  int interrupt_init (void)
  {
- 	/*
+-	/*
 -	 * setup up stacks if necessary
 -	 */
-+	 * setup up stacks if necessary*/
++	/* setup up stacks if necessary */
 +	IRQ_STACK_START = gd->irq_sp + 8;
  	IRQ_STACK_START_IN = gd->irq_sp + 8;
  
@@ -304,7 +401,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  }
  
  int global_interrupts_enabled (void)
-@@ -286,12 +306,12 @@ void enable_interrupts (void)
+@@ -286,12 +305,12 @@ void enable_interrupts (void)
  {
      unsigned long cpsr;
  	__asm__ __volatile__("mrs %0, cpsr\n"
@@ -319,7 +416,7 @@ index f817f8cd7c81..6e91b17ab186 100644
  	return;
  }
  
-@@ -304,11 +324,13 @@ int disable_interrupts (void)
+@@ -304,11 +323,13 @@ int disable_interrupts (void)
  			: "=r" (cpsr), "=r" (temp)
  			:
  			: "memory");
@@ -327,19 +424,21 @@ index f817f8cd7c81..6e91b17ab186 100644
  	return (cpsr & 0x80) == 0;
  }
  
- void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx)
+-void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx)
++void irq_install_handler(int irq, interrupt_handler_t *handler, void *cookie)
  {
 +	DBG_IRQ("  %s()\n", __FUNCTION__);
  	if (irq > max_irq) {
  		printf("irq %d out of range\n", irq);
  		return;
-@@ -317,13 +339,14 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx)
+@@ -317,19 +338,22 @@ void irq_install_handler(int irq, interrupt_handler_t *handler, void *ctx)
  		printf("irq %d already in use (%p)\n", irq, handlers[irq]);
  		return;
  	}
 -	printf("registering handler for irq %d\n", irq);
 +	DBG_IRQ("registering handler for irq %d\n", irq);
  	handlers[irq] = handler;
++	cookies[irq] = cookie;
  	enable_irq_id(irq);
  }
  
@@ -349,29 +448,36 @@ index f817f8cd7c81..6e91b17ab186 100644
  	if (irq >= max_irq) {
  		printf("irq %d out of range\n", irq);
  		return;
-@@ -338,9 +361,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
- {
+ 	}
+ 	if (handlers[irq]) {
+ 		handlers[irq] = NULL;
++		cookies[irq] = NULL;
+ 		disable_irq_id(irq);
+ 	}
+ }
+@@ -339,8 +363,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  	int i;
  	int enabled = global_interrupts_enabled();
--	printf("GIC base = 0x%x\n", gbase);
+ 	printf("GIC base = 0x%x\n", gbase);
 -	printf("interrupts %sabled\n", (enabled ? "en" : "dis"));
-+	DBG_IRQ("GIC base = 0x%x\n", gbase);
-+	DBG_IRQ("interrupts %sabled\n", (enabled ? "en" : "dis"));
++	printf("Number of interrupt sources = %d\n", max_irq);
++	printf("Interrupts %sabled\n", (enabled ? "en" : "dis"));
  	uint32_t grp_en = 0;
 +
  	for (i = 0; i < max_irq; i++) {
  		if ((i & ITLINES_MASK) == 0)
  			grp_en = gicd_readl(GICD_ISENABLERn +
-@@ -348,52 +372,28 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+@@ -348,52 +374,29 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  		int irq_enabled = grp_en & (1 << (i & ITLINES_MASK));
  		if (!irq_enabled)
  			continue;
 -		printf("% 2i (% 3s): %lu\n", i,
-+		DBG_IRQ("%2d (%3s): %lu\n", i,
++		printf("%2d (%3s): %lu\n", i,
  		       (irq_enabled ? "on" : "off"), irq_counts[i]);
  	}
 -	printf("total: %lu\n", irq_total);
-+	DBG_IRQ("total: %lu\n", irq_total);
++	printf("Total: %lu\n", irq_total);
++
  	return 0;
  }
  
@@ -414,7 +520,7 @@ index f817f8cd7c81..6e91b17ab186 100644
 -				gicd_writel(pending, GICD_ISPENDRn +
 -						(i >> ITLINES_SHIFT) * sizeof(uint32_t));
 -			}
-+	uint32_t irqstat = 0, irqnr = 0;
++	uint32_t irqstat, irqnr;
 +
 +	if (irq_total < MAX_IRQ)
 +		irq_total++;
@@ -426,10 +532,36 @@ index f817f8cd7c81..6e91b17ab186 100644
 +		if (irq_counts[irqnr] < MAX_IRQ)
 +			irq_counts[irqnr]++;
 +		if (handlers[irqnr]) {
-+			handlers[irqnr](NULL);
++			handlers[irqnr](cookies[irqnr]);
  		}
  	}
  }
+diff --git a/board/aspeed/ast2600_intel/ast-irq.h b/board/aspeed/ast2600_intel/ast-irq.h
+deleted file mode 100644
+index 9957f2baa7ff..000000000000
+--- a/board/aspeed/ast2600_intel/ast-irq.h
++++ /dev/null
+@@ -1,8 +0,0 @@
+-#ifndef _AST_IRQ_H_
+-#define _AST_IRQ_H_
+-
+-int request_irq(int irq, interrupt_handler_t *handler);
+-int release_irq(int irq);
+-int arch_interrupt_init_early(void);
+-
+-#endif
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index ac108c3a066c..22a377d2cb77 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -209,7 +209,6 @@ static void timer_handler(void *regs)
+ 	printf("+");
+ }
+ 
+-extern int arch_interrupt_init_early(void);
+ int board_early_init_f(void)
+ {
+ 	/* This is called before relocation; beware! */
 -- 
 2.7.4
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
index c737d4f95..19606ee38 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0008-AST2600-Add-TPM-pulse-trigger.patch
@@ -1,4 +1,4 @@
-From 7903cb8540f83e9beca9386681ab6232eb288527 Mon Sep 17 00:00:00 2001
+From b7f02c074c0dee6b5d6d1c1f632993f7b0e3e952 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Wed, 25 Mar 2020 15:04:26 -0700
 Subject: [PATCH] AST2600: Add TPM pulse trigger
@@ -11,10 +11,10 @@ Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
  1 file changed, 17 insertions(+)
 
 diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
-index 25c61d1a806c..cd90597221ea 100644
+index 22a377d2cb77..47e5ad21d66d 100644
 --- a/board/aspeed/ast2600_intel/intel.c
 +++ b/board/aspeed/ast2600_intel/intel.c
-@@ -193,6 +193,21 @@ static void set_gpio_default_state(void)
+@@ -204,6 +204,21 @@ static void set_gpio_default_state(void)
  	       AST_GPIO_BASE | GPIO_020);
  }
  
@@ -33,12 +33,12 @@ index 25c61d1a806c..cd90597221ea 100644
 +	       AST_GPIO_BASE | GPIO_000);
 +}
 +
- void espi_init(void);
- int arch_interrupt_init_early(void);
- 
-@@ -228,6 +243,8 @@ int board_early_init_r(void)
- 
- 	espi_init();
+ static void timer_handler(void *regs)
+ {
+ 	printf("+");
+@@ -234,6 +249,8 @@ int board_early_init_r(void)
+ 	debug("board_early_init_r\n");
+ 	/* timer_enable(0, 1, timer_handler); */
  
 +	enable_onboard_tpm();
 +
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch
new file mode 100644
index 000000000..cf13a17f2
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0010-Fix-timer-support.patch
@@ -0,0 +1,173 @@
+From bd4eb78dc71529342e5d0b784731c412cf747acc Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 20 Apr 2020 10:42:05 -0700
+Subject: [PATCH] Fix timer support
+
+Timer interrupt flag should be cleared just after it gets an
+interrupt otherwise the interrupt will be called infinitely and
+main context will starve resultingly. To fix this issue, this
+commit adds the timer interrupt flag clearing logic.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/ast-timer.c | 69 ++++++++++++++++++++--------------
+ board/aspeed/ast2600_intel/intel.c     | 13 ++++---
+ 2 files changed, 48 insertions(+), 34 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/ast-timer.c b/board/aspeed/ast2600_intel/ast-timer.c
+index cf8c69aba5d3..d98ec9238e15 100644
+--- a/board/aspeed/ast2600_intel/ast-timer.c
++++ b/board/aspeed/ast2600_intel/ast-timer.c
+@@ -1,59 +1,72 @@
+-/*
+- * Copyright 2019 Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version
+- * 2 of the License, or (at your option) any later version.
+- */
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2019-2020, Intel Corporation.
+ 
+ #include <common.h>
+ #include <asm/io.h>
+ 
+ static const int timer_irqs[] = {48, 49, 50, 51, 52, 53, 54, 55};
++static void (*timer_callback[ARRAY_SIZE(timer_irqs)]) (void *) = {NULL};
++static void *cb_cookie[ARRAY_SIZE(timer_irqs)] = {NULL};
++
+ #define AST_TIMER_BASE 0x1e782000
+ /* offsets from AST_TIMER_BASE for each timer */
+-static const uint32_t timer_bases[] = {0, 0x10, 0x20, 0x40,
+-				       0x50, 0x60, 0x70, 0x80};
+-#define TIMER_1MHZ_CLK_COUNT 1000000u
++static const u32 timer_bases[] = {0, 0x10, 0x20, 0x40, 0x50, 0x60, 0x70, 0x80};
+ #define TIMER_ENABLE 1
+ #define TIMER_1MHZ_CLK_SEL 2
+ #define TIMER_ENABLE_IRQ 4
+ #define TIMER_RESET_BY_WDT 8
+ #define TIMER_CONTROL 0x30
++#define TIMER_INT_CLR 0x34
+ #define TIMER_RELOAD 0x04
+ #define TIMER_CONTROL_CLEAR 0x3c
+ 
++static void timer_irq_handler(void *cookie)
++{
++	int timer_nr = (int)cookie;
++
++	writel(1 << timer_nr, AST_TIMER_BASE + TIMER_INT_CLR);
++
++	if (timer_callback[timer_nr])
++		timer_callback[timer_nr](cb_cookie[timer_nr]);
++}
++
+ void timer_disable(int n)
+ {
+-	if (n < 0 || n > 7) {
++	u32 tctrl;
++
++	if (n < 0 || n > 7)
+ 		return;
+-	}
+-	uint32_t tctrl = 0xf << (n * 4);
++
++	irq_free_handler(timer_irqs[n]);
++	timer_callback[n] = NULL;
++	cb_cookie[n] = NULL;
++
++	tctrl = 0xf << (n * 4);
+ 	writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL_CLEAR);
+ }
+ 
+-void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler)
++void timer_enable(uint n, u32 interval_us, interrupt_handler_t *handler,
++		  void *cookie)
+ {
+-	if (n < 0 || n > 7) {
+-		return;
+-	}
+-	if (!freq)
++	u32 tctrl;
++
++	if (n < 0 || n > 7 || !interval_us)
+ 		return;
+ 
+ 	timer_disable(n);
+ 
+-	uint32_t v = TIMER_1MHZ_CLK_COUNT / freq;
+-	writel(v, AST_TIMER_BASE + timer_bases[n] + TIMER_RELOAD);
++	writel(interval_us, AST_TIMER_BASE + timer_bases[n] + TIMER_RELOAD);
+ 
+-	uint32_t tctrl = (
+-				TIMER_ENABLE |
+-				TIMER_1MHZ_CLK_SEL |
+-				TIMER_RESET_BY_WDT) << (n * 4);
++	tctrl = (TIMER_ENABLE | TIMER_1MHZ_CLK_SEL |
++		 TIMER_RESET_BY_WDT) << (n * 4) | TIMER_ENABLE_IRQ << (n * 4);
+ 
+ 	if (handler) {
+-		irq_install_handler(timer_irqs[n], handler, NULL);
+-		tctrl |= (TIMER_ENABLE_IRQ << (n * 4));
++		timer_callback[n] = handler;
++		cb_cookie[n] = cookie;
+ 	}
+-	writel(tctrl, AST_TIMER_BASE + TIMER_CONTROL);
++
++	irq_install_handler(timer_irqs[n], timer_irq_handler, (void *)n);
++
++	writel(readl(AST_TIMER_BASE + TIMER_CONTROL) | tctrl,
++	       AST_TIMER_BASE + TIMER_CONTROL);
+ }
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index 47e5ad21d66d..befeaff0a953 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -219,16 +219,14 @@ void enable_onboard_tpm(void)
+ 	       AST_GPIO_BASE | GPIO_000);
+ }
+ 
+-static void timer_handler(void *regs)
++static void timer_callback(void *cookie)
+ {
+-	printf("+");
++	debug("+");
+ }
+ 
+ int board_early_init_f(void)
+ {
+ 	/* This is called before relocation; beware! */
+-	/* initialize running timer? timer_init is next in the list but
+-	 * I am not sure if it actually does anything... */
+ 	arch_interrupt_init_early();
+ 
+ 	set_gpio_default_state();
+@@ -243,11 +241,9 @@ int board_early_init_f(void)
+ 	return 0;
+ }
+ 
+-extern void timer_enable(int n, uint32_t freq, interrupt_handler_t *handler);
+ int board_early_init_r(void)
+ {
+ 	debug("board_early_init_r\n");
+-	/* timer_enable(0, 1, timer_handler); */
+ 
+ 	enable_onboard_tpm();
+ 
+@@ -255,8 +251,13 @@ int board_early_init_r(void)
+ }
+ 
+ extern void espi_init(void);
++extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler,
++			 void *cookie);
+ int board_late_init(void)
+ {
++#define ONE_SEC_IN_USEC		1000000
++
++	timer_enable(0, ONE_SEC_IN_USEC, timer_callback, (void *)0);
+ 	espi_init();
+ 
+ 	return 0;
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch
new file mode 100644
index 000000000..f446d797a
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0011-KCS-driver-support-in-uBoot.patch
@@ -0,0 +1,614 @@
+From 1fbd857e2ff5396ea057f686cbd01c6db4328316 Mon Sep 17 00:00:00 2001
+From: AppaRao Puli <apparao.puli@linux.intel.com>
+Date: Mon, 20 Apr 2020 11:08:22 -0700
+Subject: [PATCH] KCS driver support in uBoot
+
+Added KCS support in uBoot. This will enable
+KCS channels and set the specified registers
+to do KCS communication in uBoot. It also
+consist of read and write KCS message transations
+work flow implementation( As specified in IPMI
+specification Section 9.15). It is enabled
+only when Force Firmware Update Jumper is ON.
+
+Tested:
+Stopped booting in uBoot and sent IPMI commands
+via KCS interfaces using cmdtool.efi.
+ - Get Device ID:
+    Req: cmdtool.efi 20 18 1
+    Res: 00 23 00 12 03 02 BF 57 01 00 7B 00 00 00 00 00
+ - Get Self Test Results
+    Req: cmdtool.efi 20 18 4
+    Res: 00 56 00
+ - All other commands
+    Req: cmdtool.efi 20 18 2
+    Res: C1 (Invalid).
+
+Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com>
+Signed-off-by: James Feist <james.feist@linux.intel.com>
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/Makefile  |   1 +
+ board/aspeed/ast2600_intel/ast-kcs.c | 418 +++++++++++++++++++++++++++++++++++
+ board/aspeed/ast2600_intel/ast-kcs.h | 112 ++++++++++
+ board/aspeed/ast2600_intel/intel.c   |   4 +
+ 4 files changed, 535 insertions(+)
+ create mode 100644 board/aspeed/ast2600_intel/ast-kcs.c
+ create mode 100644 board/aspeed/ast2600_intel/ast-kcs.h
+
+diff --git a/board/aspeed/ast2600_intel/Makefile b/board/aspeed/ast2600_intel/Makefile
+index 37d2f0064f38..d049922719f3 100644
+--- a/board/aspeed/ast2600_intel/Makefile
++++ b/board/aspeed/ast2600_intel/Makefile
+@@ -2,3 +2,4 @@ obj-y += intel.o
+ obj-y += ast-espi.o
+ obj-y += ast-irq.o
+ obj-y += ast-timer.o
++obj-y += ast-kcs.o
+diff --git a/board/aspeed/ast2600_intel/ast-kcs.c b/board/aspeed/ast2600_intel/ast-kcs.c
+new file mode 100644
+index 000000000000..a03b7e725370
+--- /dev/null
++++ b/board/aspeed/ast2600_intel/ast-kcs.c
+@@ -0,0 +1,418 @@
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2018-2020 Intel Corporation
++
++#include "ast-kcs.h"
++
++#ifdef DEBUG_KCS_ENABLED
++#define DBG_KCS			printf
++#else
++#define DBG_KCS(...)
++#endif
++
++/* TODO: Move to IPMI file. */
++#define IPMI_CC_OK		0x00
++#define IPMI_CC_INVALID		0xC1
++#define IPMI_CC_UNSPECIFIED	0xFF
++
++#define KCS_CHANNEL_NO_3	3
++
++static const u16 enabled_kcs_channel[] = { KCS_CHANNEL_NO_3 };
++
++static const struct kcs_io_reg ast_kcs_bmc_ioregs[KCS_CHANNEL_MAX] = {
++	{ .idr = LPC_IDR1, .odr = LPC_ODR1, .str = LPC_STR1 },
++	{ .idr = LPC_IDR2, .odr = LPC_ODR2, .str = LPC_STR2 },
++	{ .idr = LPC_IDR3, .odr = LPC_ODR3, .str = LPC_STR3 },
++	{ .idr = LPC_IDR4, .odr = LPC_ODR4, .str = LPC_STR4 }
++};
++
++#define NO_OF_ENABLED_KCS_CHANNELS ARRAY_SIZE(enabled_kcs_channel)
++
++static struct kcs_packet m_kcs_pkt[NO_OF_ENABLED_KCS_CHANNELS];
++
++static u16 read_status(u16 channel_num)
++{
++	return readl(AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].str);
++}
++
++static void write_status(u16 channel_num, u16 value)
++{
++	writel(value, AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].str);
++}
++
++static u16 read_data(u16 channel_num)
++{
++	return readl(AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].idr);
++}
++
++static void write_data(u16 channel_num, u16 value)
++{
++	writel(value, AST_LPC_BASE + ast_kcs_bmc_ioregs[channel_num - 1].odr);
++}
++
++static void set_kcs_state(u16 channel_num, u16 state)
++{
++	u16 status = read_status(channel_num);
++
++	status &= ~KCS_STATE_MASK;
++	status |= KCS_STATE(state) & KCS_STATE_MASK;
++	write_status(channel_num, status);
++}
++
++static struct kcs_packet *get_kcs_packet(u16 channel_num)
++{
++	for (u16 idx = 0; idx < NO_OF_ENABLED_KCS_CHANNELS; idx++) {
++		if (channel_num == enabled_kcs_channel[idx])
++			return &m_kcs_pkt[idx];
++	}
++
++	/* very unlike code hits here. */
++	DBG_KCS("ERROR: %s error. ChannelNo: %d\n", __func__, channel_num);
++	BUG();
++}
++
++static void kcs_force_abort(u16 channel_num)
++{
++	struct kcs_packet *kcs_pkt = NULL;
++
++	kcs_pkt = get_kcs_packet(channel_num);
++	DBG_KCS("ERROR: KCS communication aborted (Channel:%d, Error:%d)\n",
++	       channel_num, kcs_pkt->error);
++	set_kcs_state(channel_num, KCS_STATE_ERROR);
++	read_data(channel_num);
++	write_data(channel_num, ZERO_DATA);
++
++	kcs_pkt->phase = KCS_PHASE_ERROR;
++	kcs_pkt->read_req_done = false;
++	kcs_pkt->data_in_idx = 0;
++}
++
++static void init_kcs_packet(u16 channel_num)
++{
++	struct kcs_packet *kcs_pkt = NULL;
++
++	kcs_pkt = get_kcs_packet(channel_num);
++	kcs_pkt->channel = channel_num;
++	kcs_pkt->read_req_done = false;
++	kcs_pkt->phase = KCS_PHASE_IDLE;
++	kcs_pkt->error = KCS_NO_ERROR;
++	kcs_pkt->data_in_idx = 0;
++	kcs_pkt->data_out_idx = 0;
++	kcs_pkt->data_out_len = 0;
++}
++
++static void process_kcs_request(u16 channel_num)
++{
++	struct kcs_packet *kcs_pkt = NULL;
++	int i;
++
++	kcs_pkt = get_kcs_packet(channel_num);
++	if (!kcs_pkt->read_req_done)
++		return;
++
++	DBG_KCS("%s:- chan:%d\n", __func__, channel_num);
++
++#ifdef DEBUG_KCS_ENABLED
++	DBG_KCS("Request data(Len:%d): ", kcs_pkt->data_in_idx);
++	for (i = 0; i < kcs_pkt->data_in_idx; i++)
++		DBG_KCS(" 0x%02x", kcs_pkt->data_in[i]);
++	DBG_KCS("\n");
++#endif
++
++	/*
++	 * TODO: Move it to IPMI Command Handler
++	 * Below code is added for timebeing till
++	 * we implement the IPMI command handler.
++	 */
++	kcs_pkt->data_out[0] = kcs_pkt->data_in[0]; /* netfn */
++	kcs_pkt->data_out[1] = kcs_pkt->data_in[1]; /* cmd */
++	kcs_pkt->data_out[2] = IPMI_CC_OK; /* cc */
++
++	if (((kcs_pkt->data_in[0] >> 2) == 0x06) &&
++	    (kcs_pkt->data_in[1] == 0x01)) {
++		/* Get Device ID */
++		u8 device_id[15] = { 0x23, 0x00, 0x12, 0x03, 0x02,
++				     0xBF, 0x57, 0x01, 0x00, 0x7B,
++				     0x00, 0x00, 0x00, 0x00, 0x00 };
++		for (i = 0; i < 15; i++)
++			kcs_pkt->data_out[i + 3] = device_id[i];
++		kcs_pkt->data_out_len = 18;
++	} else if (((kcs_pkt->data_in[0] >> 2) == 0x06) &&
++		   (kcs_pkt->data_in[1] == 0x04)) {
++		/* Get Self Test Results */
++		kcs_pkt->data_out[3] = 0x56;
++		kcs_pkt->data_out[4] = 0x00;
++		kcs_pkt->data_out_len = 5;
++	} else {
++		kcs_pkt->data_out[2] =
++			IPMI_CC_INVALID; /* Invalid or not supported. */
++		kcs_pkt->data_out_len = 3;
++	}
++	/* END: TODO */
++
++#ifdef DEBUG_KCS_ENABLED
++	DBG_KCS("Response data(Len:%d): ", kcs_pkt->data_out_len);
++	for (i = 0; i < kcs_pkt->data_out_len; i++)
++		DBG_KCS(" 0x%02x", kcs_pkt->data_out[i]);
++	DBG_KCS("\n");
++#endif
++
++	kcs_pkt->phase = KCS_PHASE_READ;
++	write_data(channel_num, kcs_pkt->data_out[kcs_pkt->data_out_idx++]);
++	kcs_pkt->read_req_done = false;
++}
++
++static void read_kcs_data(u16 channel_num)
++{
++	struct kcs_packet *kcs_pkt = NULL;
++
++	kcs_pkt = get_kcs_packet(channel_num);
++
++	switch (kcs_pkt->phase) {
++	case KCS_PHASE_WRITE_START:
++		kcs_pkt->phase = KCS_PHASE_WRITE_DATA;
++		/* fall through */
++
++	case KCS_PHASE_WRITE_DATA:
++		if (kcs_pkt->data_in_idx >= MAX_KCS_PKT_SIZE) {
++			kcs_pkt->error = KCS_LENGTH_ERROR;
++			kcs_force_abort(channel_num);
++			return;
++		}
++		set_kcs_state(channel_num, KCS_STATE_WRITE);
++		write_data(channel_num, ZERO_DATA);
++		kcs_pkt->data_in[kcs_pkt->data_in_idx++] =
++			read_data(channel_num);
++		break;
++
++	case KCS_PHASE_WRITE_END:
++		if (kcs_pkt->data_in_idx >= MAX_KCS_PKT_SIZE) {
++			kcs_pkt->error = KCS_LENGTH_ERROR;
++			kcs_force_abort(channel_num);
++			return;
++		}
++		set_kcs_state(channel_num, KCS_STATE_READ);
++		kcs_pkt->data_in[kcs_pkt->data_in_idx++] =
++			read_data(channel_num);
++		kcs_pkt->phase = KCS_PHASE_READ_WAIT;
++		kcs_pkt->read_req_done = true;
++
++		process_kcs_request(channel_num);
++		break;
++
++	case KCS_PHASE_READ:
++		if (kcs_pkt->data_out_idx == kcs_pkt->data_out_len)
++			set_kcs_state(channel_num, KCS_STATE_IDLE);
++
++		u8 data = read_data(channel_num);
++		if (data != KCS_CTRL_CODE_READ) {
++			DBG_KCS("Invalid Read data. Phase:%d, Data:0x%02x\n",
++				kcs_pkt->phase, data);
++			set_kcs_state(channel_num, KCS_STATE_ERROR);
++			write_data(channel_num, ZERO_DATA);
++			break;
++		}
++
++		if (kcs_pkt->data_out_idx == kcs_pkt->data_out_len) {
++			write_data(channel_num, ZERO_DATA);
++			kcs_pkt->phase = KCS_PHASE_IDLE;
++			break;
++		}
++		write_data(channel_num,
++			   kcs_pkt->data_out[kcs_pkt->data_out_idx++]);
++		break;
++
++	case KCS_PHASE_ABORT_1:
++		set_kcs_state(channel_num, KCS_STATE_READ);
++		read_data(channel_num);
++		write_data(channel_num, kcs_pkt->error);
++		kcs_pkt->phase = KCS_PHASE_ABORT_2;
++		break;
++
++	case KCS_PHASE_ABORT_2:
++		set_kcs_state(channel_num, KCS_STATE_IDLE);
++		read_data(channel_num);
++		write_data(channel_num, ZERO_DATA);
++		kcs_pkt->phase = KCS_PHASE_IDLE;
++		break;
++
++	default:
++		kcs_force_abort(channel_num);
++	}
++}
++
++static void read_kcs_cmd(u16 channel_num)
++{
++	struct kcs_packet *kcs_pkt = NULL;
++
++	kcs_pkt = get_kcs_packet(channel_num);
++
++	set_kcs_state(channel_num, KCS_STATE_WRITE);
++	write_data(channel_num, ZERO_DATA);
++
++	u16 cmd = read_data(channel_num);
++	switch (cmd) {
++	case KCS_CTRL_CODE_WRITE_START:
++		init_kcs_packet(channel_num);
++		kcs_pkt->phase = KCS_PHASE_WRITE_START;
++		break;
++
++	case KCS_CTRL_CODE_WRITE_END:
++		if (kcs_pkt->error != KCS_NO_ERROR) {
++			kcs_force_abort(channel_num);
++			return;
++		}
++
++		kcs_pkt->phase = KCS_PHASE_WRITE_END;
++		break;
++
++	case KCS_CTRL_CODE_GET_STATUS_ABORT:
++		kcs_pkt->phase = KCS_PHASE_ABORT_1;
++		kcs_pkt->error = KCS_ABORT_BY_CMD;
++		break;
++
++	default:
++		kcs_pkt->error = KCS_ILLEGAL_CTRL_CMD;
++		kcs_force_abort(channel_num);
++	}
++}
++
++static void kcs_irq_handler(void *cookie)
++{
++	u32 channel_num = (u32)cookie;
++	/* Look-up the interrupted KCS channel */
++	u16 status = read_status(channel_num);
++	if (status & BIT_STATUS_IBF) {
++		if (status & BIT_STATUS_COD)
++			read_kcs_cmd(channel_num);
++		else
++			read_kcs_data(channel_num);
++	}
++
++	DBG_KCS("%s: chan_no: %d\n", __FUNC__, channel_num);
++}
++
++static void set_kcs_channel_addr(u16 channel_num)
++{
++	u32 val;
++
++	switch (channel_num) {
++	case 1:
++		val = readl(AST_LPC_BASE + LPC_HICR4) & ~BIT_LADR12AS;
++		writel(val, AST_LPC_BASE + LPC_HICR4);
++		val = (KCS_CHANNEL1_ADDR >> 8);
++		writel(val, AST_LPC_BASE + LPC_LADR12H);
++		val = (KCS_CHANNEL1_ADDR & 0xFF);
++		writel(val, AST_LPC_BASE + LPC_LADR12L);
++		break;
++
++	case 2:
++		val = readl(AST_LPC_BASE + LPC_HICR4) | BIT_LADR12AS;
++		writel(val, AST_LPC_BASE + LPC_HICR4);
++		val = (KCS_CHANNEL2_ADDR >> 8);
++		writel(val, AST_LPC_BASE + LPC_LADR12H);
++		val = (KCS_CHANNEL2_ADDR & 0xFF);
++		writel(val, AST_LPC_BASE + LPC_LADR12L);
++		break;
++
++	case 3:
++		val = (KCS_CHANNEL3_ADDR >> 8);
++		writel(val, AST_LPC_BASE + LPC_LADR3H);
++		val = (KCS_CHANNEL3_ADDR & 0xFF);
++		writel(val, AST_LPC_BASE + LPC_LADR3L);
++		break;
++
++	case 4:
++		val = (((KCS_CHANNEL4_ADDR + 1) << 16) | KCS_CHANNEL4_ADDR);
++		writel(val, AST_LPC_BASE + LPC_LADR4);
++		break;
++
++	default:
++		DBG_KCS("Invalid channel (%d) specified\n", channel_num);
++		break;
++	}
++}
++
++static void enable_kcs_channel(u16 channel_num, u16 enable)
++{
++	u32 val;
++
++	switch (channel_num) {
++	case 1:
++		if (enable) {
++			val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE1;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++			val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC1E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++		} else {
++			val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC1E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++			val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE1;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++		}
++		break;
++
++	case 2:
++		if (enable) {
++			val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE2;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++			val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC2E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++		} else {
++			val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC2E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++			val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE2;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++		}
++		break;
++
++	case 3:
++		if (enable) {
++			val = readl(AST_LPC_BASE + LPC_HICR2) | BIT_IBFIE3;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++			val = readl(AST_LPC_BASE + LPC_HICR0) | BIT_LPC3E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++			val = readl(AST_LPC_BASE + LPC_HICR4) | BIT_KCSENBL;
++			writel(val, AST_LPC_BASE + LPC_HICR4);
++		} else {
++			val = readl(AST_LPC_BASE + LPC_HICR0) & ~BIT_LPC3E;
++			writel(val, AST_LPC_BASE + LPC_HICR0);
++			val = readl(AST_LPC_BASE + LPC_HICR4) & ~BIT_KCSENBL;
++			writel(val, AST_LPC_BASE + LPC_HICR4);
++			val = readl(AST_LPC_BASE + LPC_HICR2) & ~BIT_IBFIE3;
++			writel(val, AST_LPC_BASE + LPC_HICR2);
++		}
++		break;
++
++	case 4:
++		if (enable) {
++			val = readl(AST_LPC_BASE + LPC_HICRB) | BIT_IBFIE4 |
++			      BIT_LPC4E;
++			writel(val, AST_LPC_BASE + LPC_HICRB);
++		} else {
++			val = readl(AST_LPC_BASE + LPC_HICRB) &
++			      ~(BIT_IBFIE4 | BIT_LPC4E);
++			writel(val, AST_LPC_BASE + LPC_HICRB);
++		}
++		break;
++
++	default:
++		DBG_KCS("Invalid channel (%d) specified\n", channel_num);
++	}
++}
++
++void kcs_init(void)
++{
++	/* Initialize the KCS channels. */
++	for (u16 idx = 0; idx < NO_OF_ENABLED_KCS_CHANNELS; idx++) {
++		uint channel_num = (uint)enabled_kcs_channel[idx];
++		DBG_KCS("%s Channel: %d\n", __func__, channel_num);
++		set_kcs_channel_addr(channel_num);
++		enable_kcs_channel(channel_num, 1);
++
++		/* Set KCS channel state to idle */
++		set_kcs_state(channel_num, KCS_STATE_IDLE);
++		/* KCS interrupt */
++		irq_install_handler(IRQ_SRC_KCS_BASE + channel_num - 1,
++				    kcs_irq_handler, (void *)channel_num);
++	}
++}
+diff --git a/board/aspeed/ast2600_intel/ast-kcs.h b/board/aspeed/ast2600_intel/ast-kcs.h
+new file mode 100644
+index 000000000000..e9b949eccf69
+--- /dev/null
++++ b/board/aspeed/ast2600_intel/ast-kcs.h
+@@ -0,0 +1,112 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/* Copyright (c) 2018-2020 Intel Corporation */
++
++#include <asm/io.h>
++#include <common.h>
++
++#define KCS_CHANNEL_MAX		4
++#define IRQ_SRC_KCS_BASE	170 /* IRQ 170 */
++#define MAX_KCS_PKT_SIZE	(64 * 1024)
++/* KCS channel addresses */
++#define KCS_CHANNEL1_ADDR	0xCA0
++#define KCS_CHANNEL2_ADDR	0xCA8
++#define KCS_CHANNEL3_ADDR	0xCA2 /* KCS SMS */
++#define KCS_CHANNEL4_ADDR	0xCA4 /* KCS SMM */
++
++#define ZERO_DATA		0x00
++
++#define AST_LPC_BASE		0x1e789000
++
++/* Aspeed KCS control registers */
++#define LPC_HICR0	0x00 /* Host Interface Control Register 0 */
++#define LPC_HICR1	0x04 /* Host Interface Control Register 1 */
++#define LPC_HICR2	0x08 /* Host Interface Control Register 2 */
++#define LPC_HICR3	0x0C /* Host Interface Control Register 3 */
++#define LPC_HICR4	0x10 /* Host Interface Control Register 4 */
++#define LPC_LADR3H	0x14 /* LPC channel #3 Address Register H */
++#define LPC_LADR3L	0x18 /* LPC channel #3 Address Register H */
++#define LPC_LADR12H	0x1C /* LPC channel #1#2 Address Register H */
++#define LPC_LADR12L	0x20 /* LPC channel #1#2 Address Register L */
++#define LPC_IDR1	0x24 /* Input Data Register 1 */
++#define LPC_IDR2	0x28 /* Input Data Register 2 */
++#define LPC_IDR3	0x2C /* Input Data Register 3 */
++#define LPC_ODR1	0x30 /* Output Data Register 1 */
++#define LPC_ODR2	0x34 /* Output Data Register 2 */
++#define LPC_ODR3	0x38 /* Output Data Register 3 */
++#define LPC_STR1	0x3C /* Status Register 1 */
++#define LPC_STR2	0x40 /* Status Register 2 */
++#define LPC_STR3	0x44 /* Status Register 3 */
++#define LPC_HICRB	0x100 /* Host Interface Control Register B */
++#define LPC_LADR4	0x110 /* LPC channel #4 Address Register */
++#define LPC_IDR4	0x114 /* Input Data Register 4 */
++#define LPC_ODR4	0x118 /* Output Data Register 4 */
++#define LPC_STR4	0x11C /* Status Data Register 4 */
++
++/* LPC Bits */
++#define BIT_LADR12AS	BIT(7) /* Channel Address selection */
++#define BIT_IBFIE1	BIT(1) /* Enable IDR1 Recv completion interrupt */
++#define BIT_IBFIE2	BIT(2) /* Enable IDR2 Recv completion interrupt */
++#define BIT_IBFIE3	BIT(3) /* Enable IBF13 interrupt */
++#define BIT_LPC1E	BIT(5) /* Enable LPC channel #1 */
++#define BIT_LPC2E	BIT(6) /* Enable LPC channel #2 */
++#define BIT_LPC3E	BIT(7) /* Enable LPC channel #2 */
++#define BIT_KCSENBL	BIT(2) /* Enable KCS interface in Channel #3 */
++#define BIT_IBFIE4	BIT(1)
++#define BIT_LPC4E	BIT(0)
++
++#define BIT_STATUS_OBF	BIT(0) /* Output Data Register full #1/#2/#3 */
++#define BIT_STATUS_IBF	BIT(1) /* Input Data Register full #1/#2/#3 */
++#define BIT_STATUS_COD	BIT(3) /* Command/Data - (1=command,0=data) */
++
++#define KCS_STATE_MASK		0xC0 /* BIT[6:7] of status register */
++#define KCS_STATE(state)	((state) << 6)
++
++/* IPMI2.0(section 9.7) - KCS interface State Bits */
++#define KCS_STATE_IDLE		0x00
++#define KCS_STATE_READ		0x01
++#define KCS_STATE_WRITE		0x02
++#define KCS_STATE_ERROR		0x03
++
++/* IPMI2.0(section 9.10) - KCS interface control codes */
++#define KCS_CTRL_CODE_GET_STATUS_ABORT	0x60
++#define KCS_CTRL_CODE_WRITE_START	0x61
++#define KCS_CTRL_CODE_WRITE_END		0x62
++#define KCS_CTRL_CODE_READ		0x68
++
++struct kcs_io_reg {
++	u32 idr;
++	u32 odr;
++	u32 str;
++};
++
++enum kcs_phase {
++	KCS_PHASE_IDLE = 0,
++	KCS_PHASE_WRITE_START = 1,
++	KCS_PHASE_WRITE_DATA = 2,
++	KCS_PHASE_WRITE_END = 3,
++	KCS_PHASE_READ_WAIT = 4,
++	KCS_PHASE_READ = 5,
++	KCS_PHASE_ABORT_1 = 6,
++	KCS_PHASE_ABORT_2 = 7,
++	KCS_PHASE_ERROR = 8
++};
++
++enum kcs_error {
++	KCS_NO_ERROR = 0x00,
++	KCS_ABORT_BY_CMD = 0x01,
++	KCS_ILLEGAL_CTRL_CMD = 0x02,
++	KCS_LENGTH_ERROR = 0x06,
++	KCS_UNSPECIFIED_ERROR = 0xFF,
++};
++
++struct kcs_packet {
++	enum kcs_phase phase;
++	enum kcs_error error;
++	u16 channel;
++	bool read_req_done;
++	u16 data_in_idx;
++	u8 data_in[MAX_KCS_PKT_SIZE];
++	u16 data_out_len;
++	u16 data_out_idx;
++	u8 data_out[MAX_KCS_PKT_SIZE];
++};
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index befeaff0a953..6ac24beb930b 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -251,6 +251,7 @@ int board_early_init_r(void)
+ }
+ 
+ extern void espi_init(void);
++extern void kcs_init(void);
+ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler,
+ 			 void *cookie);
+ int board_late_init(void)
+@@ -260,6 +261,9 @@ int board_late_init(void)
+ 	timer_enable(0, ONE_SEC_IN_USEC, timer_callback, (void *)0);
+ 	espi_init();
+ 
++	if (read_ffuj())
++		kcs_init();
++
+ 	return 0;
+ }
+ 
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch
new file mode 100644
index 000000000..a4a574424
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0012-IPMI-command-handler-implementation-in-uboot.patch
@@ -0,0 +1,330 @@
+From 19bbdf59f39d295ad3e698b121a0b447b77b927c Mon Sep 17 00:00:00 2001
+From: AppaRao Puli <apparao.puli@linux.intel.com>
+Date: Mon, 20 Apr 2020 16:13:09 -0700
+Subject: [PATCH] IPMI command handler implementation in uboot
+
+IPMI command handler implementation in uBoot.
+Implemented IPMI commands:
+ 1) Get Device ID
+ 2) Get Self Test Result
+
+Tested By:
+Ran the above IPMI command Via KCS channel
+and got proper response.
+- Get Device ID
+  Req: cmdtool.efi 20 18 1
+  Res: 0x00 0x23 0x00 0x82 0x03 0x02 0x00 0x57 0x01 0x00 0x7b 0x00 0x00 0x00 0x00 0x00
+- Get Self Test Results
+  Req: cmdtool.efi 20 18 4
+  Res: 00 56 00
+
+Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com>
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/Makefile       |   1 +
+ board/aspeed/ast2600_intel/ast-kcs.c      |  77 +++++++++++---------
+ board/aspeed/ast2600_intel/ipmi-handler.c | 117 ++++++++++++++++++++++++++++++
+ board/aspeed/ast2600_intel/ipmi-handler.h |  39 ++++++++++
+ 4 files changed, 200 insertions(+), 34 deletions(-)
+ create mode 100644 board/aspeed/ast2600_intel/ipmi-handler.c
+ create mode 100644 board/aspeed/ast2600_intel/ipmi-handler.h
+
+diff --git a/board/aspeed/ast2600_intel/Makefile b/board/aspeed/ast2600_intel/Makefile
+index d049922719f3..a0587323afe0 100644
+--- a/board/aspeed/ast2600_intel/Makefile
++++ b/board/aspeed/ast2600_intel/Makefile
+@@ -3,3 +3,4 @@ obj-y += ast-espi.o
+ obj-y += ast-irq.o
+ obj-y += ast-timer.o
+ obj-y += ast-kcs.o
++obj-y += ipmi-handler.o
+diff --git a/board/aspeed/ast2600_intel/ast-kcs.c b/board/aspeed/ast2600_intel/ast-kcs.c
+index a03b7e725370..3889cd9222a4 100644
+--- a/board/aspeed/ast2600_intel/ast-kcs.c
++++ b/board/aspeed/ast2600_intel/ast-kcs.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0
+ // Copyright (c) 2018-2020 Intel Corporation
+ 
+-#include "ast-kcs.h"
++#include "ipmi-handler.h"
+ 
+ #ifdef DEBUG_KCS_ENABLED
+ #define DBG_KCS			printf
+@@ -9,11 +9,6 @@
+ #define DBG_KCS(...)
+ #endif
+ 
+-/* TODO: Move to IPMI file. */
+-#define IPMI_CC_OK		0x00
+-#define IPMI_CC_INVALID		0xC1
+-#define IPMI_CC_UNSPECIFIED	0xFF
+-
+ #define KCS_CHANNEL_NO_3	3
+ 
+ static const u16 enabled_kcs_channel[] = { KCS_CHANNEL_NO_3 };
+@@ -103,6 +98,7 @@ static void init_kcs_packet(u16 channel_num)
+ static void process_kcs_request(u16 channel_num)
+ {
+ 	struct kcs_packet *kcs_pkt = NULL;
++	struct ipmi_cmd_data ipmi_data;
+ 	int i;
+ 
+ 	kcs_pkt = get_kcs_packet(channel_num);
+@@ -117,37 +113,49 @@ static void process_kcs_request(u16 channel_num)
+ 		DBG_KCS(" 0x%02x", kcs_pkt->data_in[i]);
+ 	DBG_KCS("\n");
+ #endif
++	u8 req_lun = kcs_pkt->data_in[0] & 0x03; /* LUN[1:0]  */
++	ipmi_data.net_fun = (kcs_pkt->data_in[0] >> 2); /* netfn[7:2] */
++	ipmi_data.cmd = kcs_pkt->data_in[1]; /* cmd */
++	/* We support only BMC LUN 00h */
++	if (req_lun != LUN_BMC) {
++		kcs_pkt->data_out[0] =
++			GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun);
++		kcs_pkt->data_out[1] = ipmi_data.cmd; /* cmd */
++		kcs_pkt->data_out[2] = IPMI_CC_INVALID_CMD_LUN; /* CC code */
++		kcs_pkt->data_out_len = 3;
++		goto done;
++	}
+ 
+-	/*
+-	 * TODO: Move it to IPMI Command Handler
+-	 * Below code is added for timebeing till
+-	 * we implement the IPMI command handler.
+-	 */
+-	kcs_pkt->data_out[0] = kcs_pkt->data_in[0]; /* netfn */
+-	kcs_pkt->data_out[1] = kcs_pkt->data_in[1]; /* cmd */
+-	kcs_pkt->data_out[2] = IPMI_CC_OK; /* cc */
+-
+-	if (((kcs_pkt->data_in[0] >> 2) == 0x06) &&
+-	    (kcs_pkt->data_in[1] == 0x01)) {
+-		/* Get Device ID */
+-		u8 device_id[15] = { 0x23, 0x00, 0x12, 0x03, 0x02,
+-				     0xBF, 0x57, 0x01, 0x00, 0x7B,
+-				     0x00, 0x00, 0x00, 0x00, 0x00 };
+-		for (i = 0; i < 15; i++)
+-			kcs_pkt->data_out[i + 3] = device_id[i];
+-		kcs_pkt->data_out_len = 18;
+-	} else if (((kcs_pkt->data_in[0] >> 2) == 0x06) &&
+-		   (kcs_pkt->data_in[1] == 0x04)) {
+-		/* Get Self Test Results */
+-		kcs_pkt->data_out[3] = 0x56;
+-		kcs_pkt->data_out[4] = 0x00;
+-		kcs_pkt->data_out_len = 5;
+-	} else {
+-		kcs_pkt->data_out[2] =
+-			IPMI_CC_INVALID; /* Invalid or not supported. */
++	/* Boundary check */
++	if ((kcs_pkt->data_in_idx - 2) > sizeof(ipmi_data.req_data)) {
++		kcs_pkt->data_out[0] =
++			GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun);
++		kcs_pkt->data_out[1] = ipmi_data.cmd; /* cmd */
++		kcs_pkt->data_out[2] = IPMI_CC_OUT_OF_SPACE; /* CC code */
+ 		kcs_pkt->data_out_len = 3;
++		goto done;
+ 	}
+-	/* END: TODO */
++	/* Fill in IPMI request data */
++	ipmi_data.req_len = kcs_pkt->data_in_idx - 2;
++	for (i = 0; i < kcs_pkt->data_in_idx - 2; i++)
++		ipmi_data.req_data[i] = kcs_pkt->data_in[i + 2];
++
++	/* Call IPMI command handler */
++	ipmi_cmd_handler(&ipmi_data);
++
++	/* Get IPMI response and fill KCS out data  */
++	/* First 2 bytes in KCS response are netFn, Cmd */
++	kcs_pkt->data_out[0] = GET_RESP_NETFN_LUN(req_lun, ipmi_data.net_fun);
++	kcs_pkt->data_out[1] = ipmi_data.cmd;
++	if ((ipmi_data.res_len + 2) > sizeof(kcs_pkt->data_out)) {
++		kcs_pkt->data_out[2] = IPMI_CC_UNSPECIFIED; /* CC code */
++		kcs_pkt->data_out_len = 3;
++		goto done;
++	}
++	for (i = 0; i < ipmi_data.res_len; i++)
++		kcs_pkt->data_out[i + 2] = ipmi_data.res_data[i];
++
++	kcs_pkt->data_out_len = ipmi_data.res_len + 2;
+ 
+ #ifdef DEBUG_KCS_ENABLED
+ 	DBG_KCS("Response data(Len:%d): ", kcs_pkt->data_out_len);
+@@ -156,6 +164,7 @@ static void process_kcs_request(u16 channel_num)
+ 	DBG_KCS("\n");
+ #endif
+ 
++done:
+ 	kcs_pkt->phase = KCS_PHASE_READ;
+ 	write_data(channel_num, kcs_pkt->data_out[kcs_pkt->data_out_idx++]);
+ 	kcs_pkt->read_req_done = false;
+diff --git a/board/aspeed/ast2600_intel/ipmi-handler.c b/board/aspeed/ast2600_intel/ipmi-handler.c
+new file mode 100644
+index 000000000000..04732846ac28
+--- /dev/null
++++ b/board/aspeed/ast2600_intel/ipmi-handler.c
+@@ -0,0 +1,117 @@
++// SPDX-License-Identifier: GPL-2.0
++// Copyright (c) 2018-2020 Intel Corporation
++
++#include "ipmi-handler.h"
++
++/* IPMI network function codes */
++#define NETFN_APP			0x06
++
++/* IPMI command codes */
++#define CMD_GET_DEV_ID			0x01
++#define CMD_GET_SELF_TEST_RESULTS	0x04
++
++typedef u16 (*fun_handler)(u8 *req, u16 req_len, u8 *res);
++
++struct get_dev_id {
++	u8 completion_code;
++	u8 dev_id;
++	u8 dev_rev;
++	u8 fw_rev1;
++	u8 fw_rev2;
++	u8 ipmi_ver;
++	u8 dev_support;
++	u8 mfg_id[3];
++	u8 product_id[2];
++	u8 aux_fw_rev[4];
++};
++struct self_test_res {
++	u8 completion_code;
++	u8 res_byte[2];
++};
++
++struct ipmi_cmd_table {
++	u8 net_fun;
++	u8 cmd;
++	fun_handler process_cmd;
++};
++
++static u16 get_device_id(u8 *req, u16 req_len, u8 *res)
++{
++	/* Get Device ID */
++	bool operation = 1; /* Firmware operation */
++	u8 intel_mfg_id[3] = { 0x57, 0x01, 0x00 };
++	u8 platform_id[2] = { 0x7B, 0x00 };
++	u8 aux_fw_rev[4] = { 0x00, 0x00, 0x00, 0x00 };
++	struct get_dev_id *result = (struct get_dev_id *)res;
++
++	if (req_len != 0) {
++		result->completion_code = IPMI_CC_INVALID_DATA_LENGTH;
++		return sizeof(result->completion_code);
++	}
++
++	result->completion_code = IPMI_CC_OK;
++	result->dev_id = 0x23;
++	result->dev_rev = 0x00; /* Not provides dev SDR */
++
++	result->ipmi_ver = 0x02; /* IPMI 2.0 */
++	result->dev_support = 0x00; /* No dev support in this mode */
++	memcpy(result->mfg_id, intel_mfg_id, sizeof(result->mfg_id));
++	memcpy(result->aux_fw_rev, aux_fw_rev, sizeof(result->aux_fw_rev));
++
++	/* TODO: Get Firmware version from flash(PFM Header) */
++	result->fw_rev1 = ((operation << 7) | (0x02 & 0x7F));
++	result->fw_rev2 = 0x03;
++	/* TODO: Read Platform ID from GPIO */
++	memcpy(result->product_id, platform_id, sizeof(result->product_id));
++
++	return sizeof(struct get_dev_id);
++}
++
++static u16 get_self_test_result(u8 *req, u16 req_len, u8 *res)
++{
++	/* Get Self Test Results */
++	struct self_test_res *result = (struct self_test_res *)res;
++
++	if (req_len != 0) {
++		result->completion_code = IPMI_CC_INVALID_DATA_LENGTH;
++		return sizeof(result->completion_code);
++	}
++
++	result->completion_code = IPMI_CC_OK;
++	result->res_byte[0] = 0x56; /* Self test function not implemented. */
++	result->res_byte[1] = 0x00;
++
++	return sizeof(struct self_test_res);
++}
++
++const struct ipmi_cmd_table cmd_info[] = {
++	{ NETFN_APP,	CMD_GET_DEV_ID,			get_device_id },
++	{ NETFN_APP,	CMD_GET_SELF_TEST_RESULTS,	get_self_test_result }
++};
++
++#define CMD_TABLE_SIZE ARRAY_SIZE(cmd_info)
++
++void ipmi_cmd_handler(struct ipmi_cmd_data *ipmi_data)
++{
++	int i = 0;
++	for (i = 0; i < CMD_TABLE_SIZE; i++) {
++		if ((cmd_info[i].net_fun == ipmi_data->net_fun) &&
++		    (cmd_info[i].cmd == ipmi_data->cmd)) {
++			break;
++		}
++	}
++
++	if (i == CMD_TABLE_SIZE) {
++		/* Invalid or not supported. */
++		ipmi_data->res_data[0] = IPMI_CC_INVALID_CMD;
++		ipmi_data->res_len = 1;
++		return;
++	}
++
++	/* Call the appropriate function handler */
++	ipmi_data->res_len =
++		cmd_info[i].process_cmd(ipmi_data->req_data, ipmi_data->req_len,
++					&ipmi_data->res_data[0]);
++
++	return;
++}
+diff --git a/board/aspeed/ast2600_intel/ipmi-handler.h b/board/aspeed/ast2600_intel/ipmi-handler.h
+new file mode 100644
+index 000000000000..11a2e91fe2c2
+--- /dev/null
++++ b/board/aspeed/ast2600_intel/ipmi-handler.h
+@@ -0,0 +1,39 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/* Copyright (c) 2018-2020 Intel Corporation */
++
++#include "ast-kcs.h"
++
++/* IPMI completion codes */
++#define IPMI_CC_OK			0x00
++#define IPMI_CC_NODE_BUSY		0xC0
++#define IPMI_CC_INVALID_CMD		0xC1
++#define IPMI_CC_INVALID_CMD_LUN		0xC2
++#define IPMI_CC_OUT_OF_SPACE		0xC4
++#define IPMI_CC_INVALID_DATA_LENGTH	0xC7
++#define IPMI_CC_INVALID_DATA_FIELD	0xCC
++#define IPMI_CC_UNSPECIFIED		0xFF
++
++/* BMC IPMB LUNs */
++#define LUN_BMC				0x00
++#define LUN_OEM1			0x01
++#define LUN_SMS				0x02
++#define LUN_OEM2			0x01
++
++
++#define MAX_IPMI_REQ_DATA_SIZE		MAX_KCS_PKT_SIZE
++#define MAX_IPMI_RES_DATA_SIZE		64
++
++/* Response netFn[7:2], Lun[1:0] */
++#define GET_RESP_NETFN_LUN(lun, netfn)                                         \
++	((lun & 0x03) | (((netfn + 1) << 2) & 0xFD))
++
++struct ipmi_cmd_data {
++	u8 net_fun;
++	u8 cmd;
++	u16 req_len;
++	u16 res_len;
++	u8 req_data[MAX_IPMI_REQ_DATA_SIZE];
++	u8 res_data[MAX_IPMI_RES_DATA_SIZE];
++};
++
++void ipmi_cmd_handler(struct ipmi_cmd_data *ipmi_data);
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch
new file mode 100644
index 000000000..7d7b450a8
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch
@@ -0,0 +1,58 @@
+From 2d0a3aff4c4aa3a764958579ed10a3aab43a7d8a Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 27 Apr 2020 12:40:01 -0700
+Subject: [PATCH] Add a workaround to cover UART interrupt bug in AST2600 A0
+
+This commit adds a workaround to cover UART interrupt bug in
+AST2600 A0 revision. It makes infinite reading on the UART +0x7c
+register for clearing abnormal interrupts in every milli-second.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/intel.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c
+index 6ac24beb930b..ad5ab7632447 100644
+--- a/board/aspeed/ast2600_intel/intel.c
++++ b/board/aspeed/ast2600_intel/intel.c
+@@ -221,7 +221,19 @@ void enable_onboard_tpm(void)
+ 
+ static void timer_callback(void *cookie)
+ {
+-	debug("+");
++	uint timer_nr = (uint)cookie;
++	u32 dummy;
++
++	switch (timer_nr) {
++	case 0:
++		/* WA for UART interrupt bug in A0 */
++		dummy = readl(0x1e78307c);
++		dummy = readl(0x1e78407c);
++		dummy = readl(0x1e78d07c);
++		dummy = readl(0x1e78e07c);
++		dummy = readl(0x1e78f07c);
++		break;
++	}
+ }
+ 
+ int board_early_init_f(void)
+@@ -256,9 +268,13 @@ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler,
+ 			 void *cookie);
+ int board_late_init(void)
+ {
+-#define ONE_SEC_IN_USEC		1000000
++#define SCU_014			0x014		/* Silicon Revision ID */
++#define REV_ID_AST2600A0	0x05000303	/* AST2600 A0 */
++#define ONE_MSEC_IN_USEC	1000
++
++	if (readl(SCU_BASE | SCU_014) == REV_ID_AST2600A0)
++		timer_enable(0, ONE_MSEC_IN_USEC, timer_callback, (void *)0);
+ 
+-	timer_enable(0, ONE_SEC_IN_USEC, timer_callback, (void *)0);
+ 	espi_init();
+ 
+ 	if (read_ffuj())
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0014-Add-a-workaround-to-cover-eSPI-OOB-free-bug-in-AST26.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0014-Add-a-workaround-to-cover-eSPI-OOB-free-bug-in-AST26.patch
new file mode 100644
index 000000000..0a8333e7d
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0014-Add-a-workaround-to-cover-eSPI-OOB-free-bug-in-AST26.patch
@@ -0,0 +1,138 @@
+From 40ab08221b6f8d67d154d8f91b8e55a11d412120 Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 27 Apr 2020 17:05:09 -0700
+Subject: [PATCH] Add a workaround to cover eSPI OOB free bug in AST2600 A0
+
+This commit adds a workaround to cover eSPI OOB free bug in AST2600
+A0 revision. It enables GPIO W7 interrupt to catch eSPI reset signal
+and it sets when the reset signal is deasserted to manually set the
+OOB free bit in eSPI protocol.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ board/aspeed/ast2600_intel/ast-espi.c | 79 ++++++++++++++++++++++++++---------
+ 1 file changed, 59 insertions(+), 20 deletions(-)
+
+diff --git a/board/aspeed/ast2600_intel/ast-espi.c b/board/aspeed/ast2600_intel/ast-espi.c
+index 1d7ae529612d..a8b389f159ef 100644
+--- a/board/aspeed/ast2600_intel/ast-espi.c
++++ b/board/aspeed/ast2600_intel/ast-espi.c
+@@ -88,6 +88,7 @@
+ #define AST_ESPI_OOB_CHRDY		BIT(4)
+ #define AST_ESPI_FLASH_SW_CHRDY		BIT(7)
+ #define AST_ESPI_FLASH_SW_READ		BIT(10)
++#define AST_ESPI_SW_RESET		GENMASK(31, 24)
+ 
+ /* ESPI00C bits (Interrupt Enable) */
+ #define AST_ESPI_IEN_HW_RST		BIT(31)
+@@ -122,6 +123,7 @@
+ /* LPC chip ID */
+ #define SCR0SIO				0x170
+ #define IRQ_SRC_ESPI			74 /* IRQ 74 */
++#define IRQ_SRC_GPIO			72 /* IRQ 72 */
+ 
+ static void espi_handshake_ack(void)
+ {
+@@ -205,9 +207,9 @@ static void espi_irq_handler(void *cookie)
+ 	}
+ 
+ 	if (irq_status & AST_ESPI_HW_RST) {
+-		uint32_t v = readl(AST_ESPI_BASE + ESPI000) & 0x00ffffffff;
+-		writel(v, AST_ESPI_BASE + ESPI000);
+-		v |= 0xff000000;
++		uint32_t v;
++
++		v = readl(AST_ESPI_BASE + ESPI000) | AST_ESPI_OOB_CHRDY;
+ 		writel(v, AST_ESPI_BASE + ESPI000);
+ 
+ 		DBG_ESPI("HW_RESET\n");
+@@ -228,6 +230,56 @@ static void espi_irq_handler(void *cookie)
+ 		readl(AST_ESPI_BASE + ESPI12C), irq_status);
+ }
+ 
++static void espi_configure_irq(void)
++{
++	writel(0, AST_ESPI_BASE + ESPI110);
++	writel(0, AST_ESPI_BASE + ESPI114);
++	writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
++	       AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI118);
++	writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
++	       AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094);
++
++	writel(AST_ESPI_SUS_WARN,
++	       AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */
++	writel(0, AST_ESPI_BASE + ESPI124);
++	writel(0, AST_ESPI_BASE + ESPI128);
++	writel(AST_ESPI_SUS_WARN,
++	       AST_ESPI_BASE +
++			ESPI100); /* Enable sysev1 ints for susp warn */
++
++	writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV |
++	       AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C);
++}
++
++#define AST_GPIO_BASE		0x1e780000
++#define GPIO_148		0x148 /* GPIO U/V/W/X Interrupt Enable */
++#define GPIO_W7			BIT(23)
++#define GPIO_14C		0x14c /* GPIO U/V/W/X Sensitivity Type 0 */
++#define GPIO_150		0x150 /* GPIO U/V/W/X Sensitivity Type 1 */
++#define GPIO_154		0x154 /* GPIO U/V/W/X Sensitivity Type 2 */
++#define GPIO_158		0x158 /* GPIO U/V/W/X Interrupt Status */
++
++static void espi_reset_handler(void *cookie)
++{
++	if (readl(AST_GPIO_BASE + GPIO_158) & GPIO_W7) {
++		uint32_t v;
++
++		writel(GPIO_W7, AST_GPIO_BASE + GPIO_158);
++
++		v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_SW_RESET;
++		writel(v, AST_ESPI_BASE + ESPI000);
++		v |= AST_ESPI_SW_RESET;
++		writel(v, AST_ESPI_BASE + ESPI000);
++
++		v = readl(AST_ESPI_BASE + ESPI000) & ~AST_ESPI_OOB_CHRDY;
++		writel(v, AST_ESPI_BASE + ESPI000);
++
++		espi_configure_irq();
++
++		DBG_ESPI("eSPI Reset\n");
++	}
++}
++
+ void espi_init(void)
+ {
+ 	if (~readl(AST_SCU_BASE + AST_SCU_HW_STRAP2) &
+@@ -266,25 +318,12 @@ void espi_init(void)
+ 		       AST_ESPI_AUTO_ACK_SUS_WARN);
+ 		writel(v, AST_ESPI_BASE + ESPI080); /* Disable auto H/W ack */
+ 
+-		writel(0, AST_ESPI_BASE + ESPI110);
+-		writel(0, AST_ESPI_BASE + ESPI114);
+-		writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
+-		       AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI118);
+-		writel(AST_ESPI_HOST_RST_WARN | AST_ESPI_OOB_RST_WARN |
+-		       AST_ESPI_PLTRSTN, AST_ESPI_BASE + ESPI094);
+-
+-		writel(AST_ESPI_SUS_WARN,
+-		       AST_ESPI_BASE + ESPI120); /* int type 0 susp warn */
+-		writel(0, AST_ESPI_BASE + ESPI124);
+-		writel(0, AST_ESPI_BASE + ESPI128);
+-		writel(AST_ESPI_SUS_WARN,
+-		       AST_ESPI_BASE +
+-				ESPI100); /* Enable sysev1 ints for susp warn */
+-
+-		writel(AST_ESPI_IEN_HW_RST | AST_ESPI_IEN_SYS1_EV |
+-		       AST_ESPI_IEN_SYS_EV, AST_ESPI_BASE + ESPI00C);
++		espi_configure_irq();
+ 
+ 		irq_install_handler(IRQ_SRC_ESPI, espi_irq_handler, NULL);
++
++		irq_install_handler(IRQ_SRC_GPIO, espi_reset_handler, NULL);
++		writel(GPIO_W7, AST_GPIO_BASE + GPIO_148);
+ 	} else {
+ 		DBG_ESPI("No espi strap\n");
+ 	}
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
index 1b4201f5e..3d9d50c8d 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/0043-AST2600-PFR-u-boot-env-changes-as-per-PFR-BMC-image.patch
@@ -1,36 +1,35 @@
-From 23e29ce85056f2b296d938e1244b5b2f2160069e Mon Sep 17 00:00:00 2001
+From 948a92b3000120f902292b661a544e35d796784a Mon Sep 17 00:00:00 2001
 From: Kuiying Wang <kuiying.wang@intel.com>
-Date: Wed, 4 Mar 2020 13:21:12 +0800
-Subject: [PATCH] AST2600: PFR u-boot env changes as per PFR BMC image
+Date: Mon, 13 Apr 2020 09:30:14 +0800
+Subject: [PATCH] PFR u-boot env changes as per PFR BMC image
 
 u-boot env changes as per PFR BMC flash layout.
 
-Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
+Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 ---
- include/configs/aspeed-common.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
+ include/configs/aspeed-common.h | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
 
 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
-index 0ece4a1b94..6291e0e7d9 100644
+index 6065ec58db..b13dbd02f3 100644
 --- a/include/configs/aspeed-common.h
 +++ b/include/configs/aspeed-common.h
-@@ -53,13 +53,13 @@
-  * Miscellaneous configurable options
-  */
- #ifndef CONFIG_BOOTCOMMAND
--#define CONFIG_BOOTCOMMAND		"bootm 20080000"
-+#define CONFIG_BOOTCOMMAND		"bootm 20b00000"
+@@ -64,9 +64,11 @@
+ #define CONFIG_ENV_SIZE			0x10000
  #endif
- #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
- #define CONFIG_ENV_ADDR_REDUND
- #define CONFIG_ENV_OVERWRITE
- #define AST_FMC_CS0_BASE		0x20000000 /* CS0 */
+ 
+-#ifndef CONFIG_ENV_OFFSET
 -#define CONFIG_ENV_OFFSET		0x2400000
+-#endif
++#undef CONFIG_BOOTCOMMAND
++#define CONFIG_BOOTCOMMAND		"bootm 20b00000"
++
++#undef CONFIG_ENV_OFFSET
 +#define CONFIG_ENV_OFFSET		0xa0000
- #define CONFIG_ENV_ADDR			(AST_FMC_CS0_BASE + CONFIG_ENV_OFFSET)
- #define CONFIG_ENV_SIZE			0x10000
- #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+ 
+ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+ #define CONFIG_ENV_OVERWRITE
 -- 
-2.20.1
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
index 99ac5a220..ceaf62800 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/files/intel.cfg
@@ -11,7 +11,7 @@ CONFIG_USE_IRQ=y
 CONFIG_CMD_IRQ=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x2400000
-CONFIG_BOOTCOMMAND="bootm 20080000"
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_TARGET_EVB_AST2600A1=n
 CONFIG_PHY_NCSI=n
 CONFIG_CMD_USB=n
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
index ff1aa58e3..ae56f11eb 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
+++ b/meta-openbmc-mods/meta-ast2600/recipes-bsp/u-boot/u-boot-aspeed-sdk_%.bbappend
@@ -15,6 +15,11 @@ SRC_URI_append_intel-ast2600 = " \
     file://0007-ast2600-Override-OTP-strap-settings.patch \
     file://0008-AST2600-Add-TPM-pulse-trigger.patch \
     file://0009-AST2600-Disable-DMA-arbitration-options-on-MAC1-and-.patch \
+    file://0010-Fix-timer-support.patch \
+    file://0011-KCS-driver-support-in-uBoot.patch \
+    file://0012-IPMI-command-handler-implementation-in-uboot.patch \
+    file://0013-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch \
+    file://0014-Add-a-workaround-to-cover-eSPI-OOB-free-bug-in-AST26.patch \
     "
 
 PFR_SRC_URI = " \
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed/0001-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch b/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed/0001-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch
new file mode 100644
index 000000000..81e742412
--- /dev/null
+++ b/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed/0001-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch
@@ -0,0 +1,186 @@
+From 0177d25a23d56bca91fa7938d786b709fd7fba3e Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Mon, 27 Apr 2020 12:11:06 -0700
+Subject: [PATCH] Add a workaround to cover UART interrupt bug in AST2600 A0
+
+This commit adds a workaround to cover UART interrupt bug in
+AST2600 A0 revision. It makes infinite reading on the UART +0x7c
+register for clearing abnormal interrupts in every milli-second.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ arch/arm/boot/dts/aspeed-g6.dtsi  | 20 ++++++-------
+ drivers/tty/serial/8250/8250_of.c | 63 +++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 73 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
+index 656053386fe8..91f431e419d9 100644
+--- a/arch/arm/boot/dts/aspeed-g6.dtsi
++++ b/arch/arm/boot/dts/aspeed-g6.dtsi
+@@ -502,8 +502,8 @@
+                         };
+ 
+ 			uart1: serial@1e783000 {
+-				compatible = "ns16550a";
+-				reg = <0x1e783000 0x20>;
++				compatible = "aspeed,ast2600-uart";
++				reg = <0x1e783000 0x20>, <0x1e6e2014 0x4>, <0x1e78307c 0x4>;
+ 				reg-shift = <2>;
+ 				reg-io-width = <4>;
+ 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+@@ -516,8 +516,8 @@
+ 			};
+ 
+ 			uart5: serial@1e784000 {
+-				compatible = "ns16550a";
+-				reg = <0x1e784000 0x1000>;
++				compatible = "aspeed,ast2600-uart";
++				reg = <0x1e784000 0x20>, <0x1e6e2014 0x4>, <0x1e78407c 0x4>;
+ 				reg-shift = <2>;
+ 				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ 				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
+@@ -744,8 +744,8 @@
+ 			};
+ 
+ 			uart2: serial@1e78d000 {
+-				compatible = "ns16550a";
+-				reg = <0x1e78d000 0x20>;
++				compatible = "aspeed,ast2600-uart";
++				reg = <0x1e78d000 0x20>, <0x1e6e2014 0x4>, <0x1e78d07c 0x4>;
+ 				reg-shift = <2>;
+ 				reg-io-width = <4>;
+ 				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+@@ -758,8 +758,8 @@
+ 			};
+ 
+ 			uart3: serial@1e78e000 {
+-				compatible = "ns16550a";
+-				reg = <0x1e78e000 0x20>;
++				compatible = "aspeed,ast2600-uart";
++				reg = <0x1e78e000 0x20>, <0x1e6e2014 0x4>, <0x1e78e07c 0x4>;
+ 				reg-shift = <2>;
+ 				reg-io-width = <4>;
+ 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+@@ -772,8 +772,8 @@
+ 			};
+ 
+ 			uart4: serial@1e78f000 {
+-				compatible = "ns16550a";
+-				reg = <0x1e78f000 0x20>;
++				compatible = "aspeed,ast2600-uart";
++				reg = <0x1e78f000 0x20>, <0x1e6e2014 0x4>, <0x1e78f07c 0x4>;
+ 				reg-shift = <2>;
+ 				reg-io-width = <4>;
+ 				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
+index 9ba31701a372..53850f859424 100644
+--- a/drivers/tty/serial/8250/8250_of.c
++++ b/drivers/tty/serial/8250/8250_of.c
+@@ -16,6 +16,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/clk.h>
+ #include <linux/reset.h>
++#include <linux/workqueue.h>
+ 
+ #include "8250.h"
+ 
+@@ -24,6 +25,9 @@ struct of_serial_info {
+ 	struct reset_control *rst;
+ 	int type;
+ 	int line;
++	struct workqueue_struct *work_queue;
++	struct delayed_work work_handler;
++	void __iomem *wa_base;
+ };
+ 
+ #ifdef CONFIG_ARCH_TEGRA
+@@ -202,6 +206,18 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
+ 	return ret;
+ }
+ 
++#define WA_DELAY_JIFFIES	msecs_to_jiffies(1)
++static void clear_abnormal_int_flags(struct work_struct *work)
++{
++	struct delayed_work *dwork = to_delayed_work(work);
++	struct of_serial_info *info = container_of(dwork, struct of_serial_info,
++						   work_handler);
++
++	(void) readl(info->wa_base);
++	queue_delayed_work(info->work_queue, &info->work_handler,
++			   WA_DELAY_JIFFIES);
++}
++
+ /*
+  * Try to register a serial port
+  */
+@@ -250,6 +266,47 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
+ 	if (ret < 0)
+ 		goto err_dispose;
+ 
++	if (of_device_is_compatible(ofdev->dev.of_node,
++				    "aspeed,ast2600-uart")) {
++		#define REV_ID_AST2600A0 0x05000303
++		void __iomem *chip_id_base;
++		struct resource *res = platform_get_resource(ofdev,
++							     IORESOURCE_MEM, 1);
++
++		if (!res || resource_size(res) < 2)
++			goto skip_wa;
++
++		info->wa_base = devm_platform_ioremap_resource(ofdev, 2);
++		if (IS_ERR(info->wa_base))
++			goto skip_wa;
++
++		chip_id_base = devm_ioremap_resource(&ofdev->dev, res);
++		if (IS_ERR(chip_id_base))
++			goto skip_wa;
++
++		if (readl(chip_id_base) == REV_ID_AST2600A0) {
++			info->work_queue = alloc_ordered_workqueue(ofdev->name,
++								   0);
++			if (info->work_queue) {
++				INIT_DELAYED_WORK(&info->work_handler,
++						  clear_abnormal_int_flags);
++				queue_delayed_work(info->work_queue,
++						   &info->work_handler,
++						   WA_DELAY_JIFFIES);
++				dev_info(&ofdev->dev,
++					 "AST2600 A0 WA initiated\n");
++			} else {
++				dev_err(&ofdev->dev,
++					"Can't enable AST2600 A0 UART WA\n");
++			}
++		}
++
++		devm_iounmap(&ofdev->dev, chip_id_base);
++		devm_release_mem_region(&ofdev->dev, res->start,
++					resource_size(res));
++	}
++
++skip_wa:
+ 	info->type = port_type;
+ 	info->line = ret;
+ 	platform_set_drvdata(ofdev, info);
+@@ -271,6 +328,11 @@ static int of_platform_serial_remove(struct platform_device *ofdev)
+ {
+ 	struct of_serial_info *info = platform_get_drvdata(ofdev);
+ 
++	if (info->work_queue) {
++		cancel_delayed_work_sync(&info->work_handler);
++		destroy_workqueue(info->work_queue);
++	}
++
+ 	serial8250_unregister_port(info->line);
+ 
+ 	reset_control_assert(info->rst);
+@@ -341,6 +403,7 @@ static const struct of_device_id of_platform_serial_table[] = {
+ 		.data = (void *)PORT_XSCALE, },
+ 	{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
+ 	{ .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
++	{ .compatible = "aspeed,ast2600-uart", .data = (void *)PORT_16550A, },
+ 	{ /* end of list */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_platform_serial_table);
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed_%.bbappend
index ca534560b..d32f38611 100644
--- a/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed_%.bbappend
+++ b/meta-openbmc-mods/meta-ast2600/recipes-kernel/linux/linux-aspeed_%.bbappend
@@ -4,5 +4,7 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/linux-aspeed:"
 #LINUX_VERSION="5.2.11"
 
 # TODO: the base kernel dtsi fixups patch should be pushed upstream
-SRC_URI += "file://intel-ast2600.cfg \
-            "
+SRC_URI += " \
+    file://intel-ast2600.cfg \
+    file://0001-Add-a-workaround-to-cover-UART-interrupt-bug-in-AST2.patch \
+    "
diff --git a/meta-openbmc-mods/meta-common/classes/image_types_intel_pfr.bbclass b/meta-openbmc-mods/meta-common/classes/image_types_intel_pfr.bbclass
index 505391669..abbb0d2dc 100644
--- a/meta-openbmc-mods/meta-common/classes/image_types_intel_pfr.bbclass
+++ b/meta-openbmc-mods/meta-common/classes/image_types_intel_pfr.bbclass
@@ -72,6 +72,8 @@ do_image_pfr () {
     mv ${PFR_IMAGES_DIR}/bmc_unsigned_cap.bin ${PFR_IMAGES_DIR}/bmc_unsigned_cap-${DATETIME}.bin
     mv ${PFR_IMAGES_DIR}/bmc_signed_cap.bin ${PFR_IMAGES_DIR}/bmc_signed_cap-${DATETIME}.bin
     mv ${PFR_IMAGES_DIR}/image-mtd-pfr ${PFR_IMAGES_DIR}/image-mtd-pfr-${DATETIME}.bin
+    ln -sf ${PFR_IMAGES_DIR}/image-mtd-pfr-${DATETIME}.bin ${PFR_IMAGES_DIR}/image-mtd-pfr.bin
+    ln -sf ${PFR_IMAGES_DIR}/bmc_signed_cap-${DATETIME}.bin ${PFR_IMAGES_DIR}/bmc_signed_cap.bin
 }
 
 do_image_pfr[vardepsexclude] += "DATE DATETIME"
diff --git a/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass b/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
index ceee7f0fc..4d50fbc52 100644
--- a/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
+++ b/meta-openbmc-mods/meta-common/classes/obmc-phosphor-image-common.bbclass
@@ -42,7 +42,6 @@ IMAGE_INSTALL_append = " \
         nv-sync \
         security-manager \
         multi-node-nl \
-        mctpd \
         virtual-media \
         enable-nics \
         host-misc-comm-manager \
diff --git a/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/dev-only.cfg b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/dev-only.cfg
new file mode 100644
index 000000000..f8f49e001
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/dev-only.cfg
@@ -0,0 +1,4 @@
+CONFIG_NC=y
+CONFIG_NETSTAT=y
+CONFIG_TFTP=y
+CONFIG_WGET=y
diff --git a/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/disable.cfg b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/disable.cfg
new file mode 100644
index 000000000..2550ffaf5
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox/disable.cfg
@@ -0,0 +1,6 @@
+CONFIG_NC=n
+CONFIG_NETSTAT=n
+CONFIG_TELNET=n
+CONFIG_TFTP=n
+CONFIG_WGET=n
+CONFIG_UDHCPD=n
diff --git a/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox_%.bbappend b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox_%.bbappend
new file mode 100644
index 000000000..deb9ccbf8
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-core/busybox/busybox_%.bbappend
@@ -0,0 +1,4 @@
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+SRC_URI += "file://disable.cfg"
+
+SRC_URI += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'debug-tweaks','file://dev-only.cfg','',d)}"
diff --git a/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend b/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
index 16ee0b625..5fda8788e 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-core/ipmi/intel-ipmi-oem_%.bbappend
@@ -2,4 +2,4 @@ EXTRA_OECMAKE += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', '-DINTEL_PF
 EXTRA_OECMAKE += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'validation-unsecure', '-DBMC_VALIDATION_UNSECURE_FEATURE=ON', '', d)}"
 EXTRA_OECMAKE += "-DUSING_ENTITY_MANAGER_DECORATORS=OFF"
 SRC_URI = "git://github.com/openbmc/intel-ipmi-oem.git"
-SRCREV = "2b664d5a185247f0448c763ba7d0e42cfc245024"
+SRCREV = "899bfd15e7230b5da0b2b16c814f4e3bdf6c824c"
diff --git a/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service b/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
index f5210dd5b..bad3329d3 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
+++ b/meta-openbmc-mods/meta-common/recipes-core/nv-sync/nv-sync/nv-sync.service
@@ -6,6 +6,8 @@ Description=Overlay sync to NV storage
 ExecStart=bash -c 'while true; do rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay; sync /tmp/.rwfs/.overlay; sleep 10; done'
 # On shutdown, archive the bash history so we don't lose it and run one last sync
 ExecStop=bash -c 'history -a; rsync -a --delete /tmp/.overlay/ /tmp/.rwfs/.overlay; sync /tmp/.rwfs/.overlay; sleep 5'
+# Due to sync delay stopping this service will take more than default 10 seconds
+TimeoutStopSec=20
 
 [Install]
 WantedBy=multi-user.target
diff --git a/meta-openbmc-mods/meta-common/recipes-core/os-release/version-vars.inc b/meta-openbmc-mods/meta-common/recipes-core/os-release/version-vars.inc
index 0c8f3be56..95061a570 100644
--- a/meta-openbmc-mods/meta-common/recipes-core/os-release/version-vars.inc
+++ b/meta-openbmc-mods/meta-common/recipes-core/os-release/version-vars.inc
@@ -53,11 +53,14 @@ python() {
                          'describe --long --abbrev=6 ' +
                          '--match \'{}-[0-9]*\.[0-9]*\''.format(gen))
 
-    # Until tags in meta-openbmc-mods, interim measure keep builds working.
+    # If no tag in meta-openbmc-mods, provide default version
     if meta_vers.startswith('fatal:'):
         meta_vers = '{}-0.0-0'.format(gen)
 
     meta_hash = irun_git(d, mibase, 'rev-parse HEAD')
+    # If no hash from meta-openbmc-mods, provide default
+    if meta_hash.startswith('fatal:'):
+        meta_hash = '00000000'
     version_id = '{}-{}'.format(meta_vers, obmc_hash[0:7])
     if version_id:
         d.setVar('VERSION_ID', version_id)
diff --git a/meta-openbmc-mods/meta-common/recipes-devtools/mtd-util/mtd-util.bb b/meta-openbmc-mods/meta-common/recipes-devtools/mtd-util/mtd-util.bb
index 7e9d2f195..32bfba4b6 100644
--- a/meta-openbmc-mods/meta-common/recipes-devtools/mtd-util/mtd-util.bb
+++ b/meta-openbmc-mods/meta-common/recipes-devtools/mtd-util/mtd-util.bb
@@ -11,7 +11,7 @@ SRCREV = "69016601a521a95732cc49a3f4c8c7fe4b0ee058"
 
 S = "${WORKDIR}/git"
 
-DEPENDS += "dbus openssl zlib boost microsoft-gsl"
+DEPENDS += "dbus systemd sdbusplus openssl zlib boost microsoft-gsl i2c-tools"
 
 inherit cmake pkgconfig
 
diff --git a/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend b/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
index 741ac3715..2f877ed53 100644
--- a/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-graphics/libvncserver/libvncserver_%.bbappend
@@ -1,5 +1,5 @@
 FILESEXTRAPATHS_append := ":${THISDIR}/${PN}"
 
 # Use the latest to support obmc-ikvm properly
-#SRC_URI = "git://github.com/LibVNC/libvncserver"
-SRCREV = "9409a6e6aaeaff9dc36f71c21ba5b81b10d44ace"
+SRC_URI = "git://github.com/LibVNC/libvncserver;nobranch=1"
+SRCREV = "ce9ae99b370d76521add190a8ca593aa6e3114dd"
diff --git a/meta-openbmc-mods/meta-common/recipes-intel/host-misc-comm-manager/host-misc-comm-manager_git.bb b/meta-openbmc-mods/meta-common/recipes-intel/host-misc-comm-manager/host-misc-comm-manager_git.bb
index 604ee8068..0a07f5ab0 100644
--- a/meta-openbmc-mods/meta-common/recipes-intel/host-misc-comm-manager/host-misc-comm-manager_git.bb
+++ b/meta-openbmc-mods/meta-common/recipes-intel/host-misc-comm-manager/host-misc-comm-manager_git.bb
@@ -11,7 +11,7 @@ LIC_FILES_CHKSUM = "file://LICENSE;md5=e3fc50a88d0a364313df4b21ef20c29e"
 
 SRC_URI = "git://github.com/Intel-BMC/host-misc-comm-manager.git;protocol=ssh"
 
-SRCREV = "2f7be710dea914b975bfb20a9d7a466da85f88cc"
+SRCREV = "7e14ddf805cda0cdf3db564081144d9532e555cd"
 
 inherit cmake systemd
 SYSTEMD_SERVICE_${PN} = "xyz.openbmc_project.Host.Misc.Manager.service"
diff --git a/meta-openbmc-mods/meta-common/recipes-intel/hsbp/hsbp-manager_git.bb b/meta-openbmc-mods/meta-common/recipes-intel/hsbp/hsbp-manager_git.bb
index b6fa1c9ea..47e2d7c46 100644
--- a/meta-openbmc-mods/meta-common/recipes-intel/hsbp/hsbp-manager_git.bb
+++ b/meta-openbmc-mods/meta-common/recipes-intel/hsbp/hsbp-manager_git.bb
@@ -2,7 +2,7 @@ SUMMARY = "HSBP Manager"
 DESCRIPTION = "HSBP Manager monitors HSBPs through SMBUS"
 
 SRC_URI = "git://github.com/openbmc/s2600wf-misc.git"
-SRCREV = "da0c35fce8b53c1fba05b253c2e24effbbd97197"
+SRCREV = "d86629cedb04607301eef6220688c53f0b29ea0e"
 PV = "0.1+git${SRCPV}"
 
 LICENSE = "Apache-2.0"
diff --git a/meta-openbmc-mods/meta-common/recipes-intel/intel-pfr/intel-blocksign-native.bb b/meta-openbmc-mods/meta-common/recipes-intel/intel-pfr/intel-blocksign-native.bb
index 9f8100dc2..4f72dbe2b 100644
--- a/meta-openbmc-mods/meta-common/recipes-intel/intel-pfr/intel-blocksign-native.bb
+++ b/meta-openbmc-mods/meta-common/recipes-intel/intel-pfr/intel-blocksign-native.bb
@@ -8,7 +8,7 @@ LIC_FILES_CHKSUM = "file://${INTELBASE}/COPYING.apache-2.0;md5=34400b68072d710fe
 
 DEPENDS = "openssl-native libxml2-native "
 
-SRC_URI = "git://github.com/Intel-BMC/blocksign;protocol=ssh"
+SRC_URI = "git://git@github.com/Intel-BMC/blocksign;protocol=ssh"
 
 SRCREV = "852d88a1cbf4dc5856ff88e823a38d2872a86ffe"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-intel/smbios/smbios-mdrv2/smbios-mdrv2.service b/meta-openbmc-mods/meta-common/recipes-intel/smbios/smbios-mdrv2/smbios-mdrv2.service
index b72873406..342d17b13 100644
--- a/meta-openbmc-mods/meta-common/recipes-intel/smbios/smbios-mdrv2/smbios-mdrv2.service
+++ b/meta-openbmc-mods/meta-common/recipes-intel/smbios/smbios-mdrv2/smbios-mdrv2.service
@@ -5,6 +5,7 @@ Description=Intel BMC SMBIOS MDR V2
 Restart=always
 RestartSec=5
 StartLimitBurst=10
+ExecStartPre=/bin/mkdir -p /var/lib/smbios
 ExecStart=/usr/bin/env smbiosmdrv2app
 SyslogIdentifier=smbiosmdrv2app
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
index 5a01aaeed..5c4fb8a25 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2500-platforms.patch
@@ -1,4 +1,4 @@
-From c2019bbf210e0e750478a3e6c0c9bfa557c5bc0f Mon Sep 17 00:00:00 2001
+From 2399c5d353e4b8dc55bd7c56bb3f1d01918bccd9 Mon Sep 17 00:00:00 2001
 From: Yuan Li <yuan.li@linux.intel.com>
 Date: Tue, 19 Sep 2017 15:55:39 +0800
 Subject: [PATCH] arm: dts: add DTS for Intel ast2500 platforms
@@ -16,17 +16,18 @@ Signed-off-by: Chen Yugang <yugang.chen@linux.intel.com>
 Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
 Signed-off-by: jayaprakash Mutyala <mutyalax.jayaprakash@intel.com>
 Signed-off-by: AppaRao Puli <apparao.puli@linux.intel.com>
+Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
- arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts | 474 +++++++++++++++++++++++++
- 1 file changed, 474 insertions(+)
+ .../arm/boot/dts/aspeed-bmc-intel-ast2500.dts | 477 ++++++++++++++++++
+ 1 file changed, 477 insertions(+)
  create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
 new file mode 100644
-index 000000000000..18fa1f804874
+index 000000000000..980e2b55a09a
 --- /dev/null
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
-@@ -0,0 +1,468 @@
+@@ -0,0 +1,477 @@
 +/dts-v1/;
 +
 +#include "aspeed-g5.dtsi"
@@ -255,6 +256,15 @@ index 000000000000..18fa1f804874
 +	status = "okay";
 +};
 +
++&sio_regs {
++	status = "okay";
++	sio_status {
++		offset = <0x8C>;
++		bit-mask = <0x1F>;
++		bit-shift = <4>;
++	};
++};
++
 +&lpc_sio {
 +	status = "okay";
 +};
@@ -496,5 +506,5 @@ index 000000000000..18fa1f804874
 +	status = "okay";
 +};
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
index b3e7342c5..e77f744ff 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0001-arm-dts-add-DTS-for-Intel-ast2600-platforms.patch
@@ -1,4 +1,4 @@
-From 0fca4f924e45f1968f610ad8903f18d638188784 Mon Sep 17 00:00:00 2001
+From 297e22a00a71d386c93b1e0d587a01c0386b31f3 Mon Sep 17 00:00:00 2001
 From: Vernon Mauery <vernon.mauery@linux.intel.com>
 Date: Tue, 19 Sep 2017 15:55:39 +0800
 Subject: [PATCH] arm: dts: add DTS for Intel ast2600 platforms
@@ -11,17 +11,18 @@ Signed-off-by: Chen Yugang <yugang.chen@linux.intel.com>
 Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 Signed-off-by: arun-pm <arun.p.m@linux.intel.com>
 Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com>
+Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
- arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 516 +++++++++++++++++++++++++
- 1 file changed, 516 insertions(+)
+ .../arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 519 ++++++++++++++++++
+ 1 file changed, 519 insertions(+)
  create mode 100644 arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
 new file mode 100644
-index 000000000000..6d626338232e
+index 000000000000..a95b5ac828b3
 --- /dev/null
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
-@@ -0,0 +1,510 @@
+@@ -0,0 +1,519 @@
 +// SPDX-License-Identifier: GPL-2.0+
 +/dts-v1/;
 +
@@ -279,6 +280,15 @@ index 000000000000..6d626338232e
 +	status = "okay";
 +};
 +
++&sio_regs {
++	status = "okay";
++	sio_status {
++		offset = <0x8C>;
++		bit-mask = <0x1F>;
++		bit-shift = <4>;
++	};
++};
++
 +&lpc_sio {
 +	status = "okay";
 +};
@@ -533,5 +543,5 @@ index 000000000000..6d626338232e
 +	status = "okay";
 +};
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch
index ca54df9ee..7dd9990a9 100644..100755
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0005-128MB-flashmap-for-PFR.patch
@@ -1,6 +1,6 @@
-From 9a71adc7aecbfdf066ba54c763c2ecd8fb09d3cd Mon Sep 17 00:00:00 2001
-From: Vikram Bodireddy <vikram.bodireddy@intel.com>
-Date: Wed, 6 Feb 2019 15:59:34 +0530
+From ca0fa975d066b15637188e8fe37dd6d12e0e2bc4 Mon Sep 17 00:00:00 2001
+From: Kuiying Wang <kuiying.wang@intel.com>
+Date: Tue, 28 Apr 2020 22:32:41 +0800
 Subject: [PATCH] Selecting 128MB for PFR
 
 PFR platforms requires 128MB flash mapping.
@@ -8,15 +8,17 @@ This will override the existing 64MB flash map
 and loads 128MB flash map.
 
 Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
+Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
 ---
  arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
+ arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
-index 4815104459f1..df02bb1aaf36 100644
+index 13b94bdf5d62..2cab5fb38d4f 100644
 --- a/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
 +++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2500.dts
-@@ -89,7 +89,7 @@
+@@ -96,7 +96,7 @@
  	flash@0 {
  		status = "okay";
  		m25p,fast-read;
@@ -25,6 +27,19 @@ index 4815104459f1..df02bb1aaf36 100644
  	};
  };
  
+diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
+index a95b5ac828b3..bf66e1b6c0fd 100644
+--- a/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
++++ b/arch/arm/boot/dts/aspeed-bmc-intel-ast2600.dts
+@@ -94,7 +94,7 @@
+ 		spi-max-frequency = <40000000>;
+ 		spi-tx-bus-width = <4>;
+ 		m25p,fast-read;
+-#include "openbmc-flash-layout-intel-64MB.dtsi"
++#include "openbmc-flash-layout-intel-128MB.dtsi"
+ 	};
+ };
+ 
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch
index 4d7440185..ef234fffe 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0103-Refine-clock-settings.patch
@@ -1,4 +1,4 @@
-From dd7498a847b3e908dabaed2e9a27b43a26d0dba0 Mon Sep 17 00:00:00 2001
+From 9fc2343bac42db2432f96db1bbfc6979822a7154 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Thu, 26 Mar 2020 14:20:19 -0700
 Subject: [PATCH] Refine clock settings
@@ -8,11 +8,11 @@ code from Aspeed SDK v00.05.05
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 ---
- drivers/clk/clk-ast2600.c | 104 +++++++++++++++++++++++++++++++++++++---------
- 1 file changed, 85 insertions(+), 19 deletions(-)
+ drivers/clk/clk-ast2600.c | 60 +++++++++++++++++++++++++++++++++++++++++------
+ 1 file changed, 53 insertions(+), 7 deletions(-)
 
 diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
-index af908b2dbeb6..e5079c5f4fcf 100644
+index fb6b11440b97..e07326544fdc 100644
 --- a/drivers/clk/clk-ast2600.c
 +++ b/drivers/clk/clk-ast2600.c
 @@ -31,6 +31,24 @@
@@ -86,69 +86,7 @@ index af908b2dbeb6..e5079c5f4fcf 100644
  			&aspeed_g6_clk_lock);
  	if (IS_ERR(hw))
  		return PTR_ERR(hw);
-@@ -650,12 +665,20 @@ static struct platform_driver aspeed_g6_clk_driver = {
- };
- builtin_platform_driver(aspeed_g6_clk_driver);
- 
--static const u32 ast2600_a0_axi_ahb_div_table[] = {
--	2, 2, 3, 5,
-+static u32 ast2600_a0_axi_ahb_div_table[] = {
-+	2, 2, 3, 4,
- };
- 
--static const u32 ast2600_a1_axi_ahb_div_table[] = {
--	4, 6, 2, 4,
-+static u32 ast2600_a1_axi_ahb_div0_table[] = {
-+	3, 2, 3, 4,
-+};
-+
-+static u32 ast2600_a1_axi_ahb_div1_table[] = {
-+	3, 4, 6, 8,
-+};
-+
-+static const u32 ast2600_a1_axi_ahb_default_table[] = {
-+	3, 4, 3, 4, 2, 2, 2, 2,
- };
- 
- static void __init aspeed_g6_cc(struct regmap *map)
-@@ -686,16 +709,28 @@ static void __init aspeed_g6_cc(struct regmap *map)
- 
- 	/* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
- 	regmap_read(map, ASPEED_G6_STRAP1, &val);
--	if (val & BIT(16))
--		axi_div = 1;
--	else
--		axi_div = 2;
--
- 	regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
--	if (chip_id & BIT(16))
--		ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
--	else
-+	if (chip_id & BIT(16)) {
-+		if (val & BIT(16)) {
-+			axi_div = 1;
-+			ast2600_a1_axi_ahb_div1_table[0] =
-+				ast2600_a1_axi_ahb_default_table[(val >> 8) &
-+								 0x3];
-+			ahb_div = ast2600_a1_axi_ahb_div1_table[(val >> 11) &
-+								0x3];
-+		} else {
-+			axi_div = 2;
-+			ast2600_a1_axi_ahb_div0_table[0] =
-+				ast2600_a1_axi_ahb_default_table[(val >> 8) &
-+								 0x3];
-+			ahb_div = ast2600_a1_axi_ahb_div0_table[(val >> 11) &
-+								0x3];
-+		}
-+	} else {
-+		/* a0 : fix axi = hpll/2 */
-+		axi_div = 2;
- 		ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
-+	}
- 
- 	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
- 	aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
-@@ -751,6 +786,37 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
+@@ -770,6 +785,37 @@ static void __init aspeed_g6_cc_init(struct device_node *np)
  		return;
  	}
  
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch
index f366287f1..ec215d07a 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0104-Add-chip-unique-id-reading-interface.patch
@@ -1,4 +1,4 @@
-From 61fd1c976a0867deec8607183849969e2d96aef7 Mon Sep 17 00:00:00 2001
+From 766f7e504cc2a0508c887c7625332c88f93c5729 Mon Sep 17 00:00:00 2001
 From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Date: Fri, 27 Mar 2020 14:42:05 -0700
 Subject: [PATCH] Add chip unique id reading interface
@@ -8,12 +8,13 @@ Optionally, the id can be encrypted using a dts-supplied hash data.
 
 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
 Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
+Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
 ---
  drivers/soc/aspeed/aspeed-bmc-misc.c | 118 ++++++++++++++++++++++++---
  1 file changed, 105 insertions(+), 13 deletions(-)
 
 diff --git a/drivers/soc/aspeed/aspeed-bmc-misc.c b/drivers/soc/aspeed/aspeed-bmc-misc.c
-index 04d97ab17274..c80b2e71f254 100644
+index 04d97ab17274..4aad3129f793 100644
 --- a/drivers/soc/aspeed/aspeed-bmc-misc.c
 +++ b/drivers/soc/aspeed/aspeed-bmc-misc.c
 @@ -7,15 +7,18 @@
@@ -52,7 +53,7 @@ index 04d97ab17274..c80b2e71f254 100644
  	 *     label = "foo";
  	 * }
  	 */
-@@ -48,9 +53,22 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
+@@ -48,9 +53,21 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
  	if (rc < 0)
  		return rc;
  
@@ -74,15 +75,13 @@ index 04d97ab17274..c80b2e71f254 100644
 +		if (rc < 0)
 +			return rc;
 +	}
-+	ctrl->mask <<= ctrl->shift;
  
  	rc = of_property_read_u32(child, "bit-shift", &ctrl->shift);
  	if (rc < 0)
-@@ -58,7 +76,9 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
- 
+@@ -59,6 +76,9 @@ static int aspeed_bmc_misc_parse_dt_child(struct device_node *child,
  	ctrl->read_only = of_property_read_bool(child, "read-only");
  
--	ctrl->mask <<= ctrl->shift;
+ 	ctrl->mask <<= ctrl->shift;
 +	/* optional hash_data for obfuscating reads */
 +	if (of_property_read_string(child, "hash-data", &ctrl->hash_data))
 +		ctrl->hash_data = NULL;
@@ -188,7 +187,7 @@ index 04d97ab17274..c80b2e71f254 100644
  }
  
  static ssize_t aspeed_bmc_misc_store(struct kobject *kobj,
-@@ -114,15 +206,15 @@ static ssize_t aspeed_bmc_misc_store(struct kobject *kobj,
+@@ -114,17 +206,17 @@ static ssize_t aspeed_bmc_misc_store(struct kobject *kobj,
  	long val;
  	int rc;
  
@@ -206,8 +205,11 @@ index 04d97ab17274..c80b2e71f254 100644
 +		return rc;
 +
  	val <<= ctrl->shift;
- 	rc = regmap_update_bits(ctrl->map, ctrl->offset, ctrl->mask, val);
+-	rc = regmap_update_bits(ctrl->map, ctrl->offset, ctrl->mask, val);
++	rc = regmap_write_bits(ctrl->map, ctrl->offset, ctrl->mask, val);
  
+ 	return rc < 0 ? rc : count;
+ }
 -- 
 2.17.1
 
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0105-i2c-aspeed-fix-arbitration-loss-handling-logic.patch b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0105-i2c-aspeed-fix-arbitration-loss-handling-logic.patch
new file mode 100644
index 000000000..f5c0a6ec8
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed/0105-i2c-aspeed-fix-arbitration-loss-handling-logic.patch
@@ -0,0 +1,38 @@
+From 2cf0bee18a390a90cd1e5736ba79909a8feef94e Mon Sep 17 00:00:00 2001
+From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+Date: Tue, 28 Apr 2020 12:08:14 -0700
+Subject: [PATCH] i2c: aspeed: fix arbitration loss handling logic
+
+When an arbitration loss happens in a multi-master bus, driver
+drops the packet induce I2C subsystem to retry the transaction
+by returning -EAGAIN. During this handling, tx_ack comes along
+sometimes and it causes this this garbage printing
+out:
+
+aspeed-i2c-bus 1e78a400.i2c-bus: irq handled != irq. expected 0x00000009, but was 0x00000008
+
+To fix this issue, this commit adds the tx_ack flag clearing into
+the arbitration loss handling logic.
+
+Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
+---
+ drivers/i2c/busses/i2c-aspeed.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c
+index b56e60508914..8625c0da440b 100644
+--- a/drivers/i2c/busses/i2c-aspeed.c
++++ b/drivers/i2c/busses/i2c-aspeed.c
+@@ -896,6 +896,9 @@ static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
+ 		if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
+ 			bus->cmd_err = ret;
+ 			bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
++			if (ret == -EAGAIN)
++				irq_handled |= (irq_status &
++						ASPEED_I2CD_INTR_TX_ACK);
+ 			goto out_complete;
+ 		}
+ 	}
+-- 
+2.7.4
+
diff --git a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
index 936ea4100..1f3085503 100644
--- a/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-kernel/linux/linux-aspeed_%.bbappend
@@ -75,6 +75,7 @@ SRC_URI += " \
         file://0102-Fix-for-dirty-node-in-jffs2-summary-entry.patch \
         file://0103-Refine-clock-settings.patch \
         file://0104-Add-chip-unique-id-reading-interface.patch \
+        file://0105-i2c-aspeed-fix-arbitration-loss-handling-logic.patch \
         "
 
 SRC_URI += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', 'file://0005-128MB-flashmap-for-PFR.patch', '', d)}"
diff --git a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch b/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch
index 596dfce48..1b36e9d77 100644
--- a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch
+++ b/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch
@@ -1,4 +1,4 @@
-From 163c1756ee676859622614996be81393eb348220 Mon Sep 17 00:00:00 2001
+From 8aee963295f7da07ae67aa09c4eba3fbd2a6ff19 Mon Sep 17 00:00:00 2001
 From: Johnathan Mantey <johnathanx.mantey@intel.com>
 Date: Thu, 30 Jan 2020 15:07:39 -0800
 Subject: [PATCH] Enhance DHCP beyond just OFF and IPv4/IPv6 enabled.
@@ -32,6 +32,8 @@ DHCP.
 
 Change-Id: I2e0ff80ac3a5e88bcff28adac419bf21e37be162
 Signed-off-by: Johnathan Mantey <johnathanx.mantey@intel.com>
+
+%% original patch: 0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch
 ---
  Makefile.am                      |   1 +
  configure.ac                     |   1 +
@@ -71,7 +73,7 @@ index 12d6caa..fed3e09 100644
  # Checks for header files.
  AC_CHECK_HEADER(systemd/sd-bus.h, ,\
 diff --git a/ethernet_interface.cpp b/ethernet_interface.cpp
-index fca86bd..3fb0f5e 100644
+index d6c7bdd..82716f9 100644
 --- a/ethernet_interface.cpp
 +++ b/ethernet_interface.cpp
 @@ -3,7 +3,6 @@
@@ -82,7 +84,7 @@ index fca86bd..3fb0f5e 100644
  #include "neighbor.hpp"
  #include "network_manager.hpp"
  #include "vlan_interface.hpp"
-@@ -62,10 +61,12 @@ struct EthernetIntfSocket
+@@ -69,10 +68,12 @@ struct EthernetIntfSocket
  
      int sock{-1};
  };
@@ -96,7 +98,7 @@ index fca86bd..3fb0f5e 100644
                                       bool emitSignal) :
      Ifaces(bus, objPath.c_str(), true),
      bus(bus), manager(parent), objPath(objPath)
-@@ -112,6 +113,65 @@ static IP::Protocol convertFamily(int family)
+@@ -119,6 +120,65 @@ static IP::Protocol convertFamily(int family)
      throw std::invalid_argument("Bad address family");
  }
  
@@ -162,7 +164,7 @@ index fca86bd..3fb0f5e 100644
  void EthernetInterface::createIPAddressObjects()
  {
      addrs.clear();
-@@ -122,7 +182,7 @@ void EthernetInterface::createIPAddressObjects()
+@@ -129,7 +189,7 @@ void EthernetInterface::createIPAddressObjects()
      {
          IP::Protocol addressType = convertFamily(addr.addrType);
          IP::AddressOrigin origin = IP::AddressOrigin::Static;
@@ -171,7 +173,7 @@ index fca86bd..3fb0f5e 100644
          {
              origin = IP::AddressOrigin::DHCP;
          }
-@@ -183,11 +243,11 @@ ObjectPath EthernetInterface::iP(IP::Protocol protType, std::string ipaddress,
+@@ -190,11 +250,11 @@ ObjectPath EthernetInterface::iP(IP::Protocol protType, std::string ipaddress,
                                   uint8_t prefixLength, std::string gateway)
  {
  
@@ -185,7 +187,7 @@ index fca86bd..3fb0f5e 100644
      }
  
      IP::AddressOrigin origin = IP::AddressOrigin::Static;
-@@ -460,7 +520,7 @@ bool EthernetInterface::iPv6AcceptRA(bool value)
+@@ -469,7 +529,7 @@ bool EthernetInterface::iPv6AcceptRA(bool value)
      return value;
  }
  
@@ -194,7 +196,7 @@ index fca86bd..3fb0f5e 100644
  {
      if (value == EthernetInterfaceIntf::dHCPEnabled())
      {
-@@ -552,7 +612,7 @@ void EthernetInterface::loadVLAN(VlanId id)
+@@ -685,7 +745,7 @@ void EthernetInterface::loadVLAN(VlanId id)
      std::string path = objPath;
      path += "_" + std::to_string(id);
  
@@ -203,7 +205,7 @@ index fca86bd..3fb0f5e 100644
          getDHCPValue(manager.getConfDir().string(), vlanInterfaceName);
  
      auto vlanIntf = std::make_unique<phosphor::network::VlanInterface>(
-@@ -574,7 +634,8 @@ ObjectPath EthernetInterface::createVLAN(VlanId id)
+@@ -707,7 +767,8 @@ ObjectPath EthernetInterface::createVLAN(VlanId id)
      path += "_" + std::to_string(id);
  
      auto vlanIntf = std::make_unique<phosphor::network::VlanInterface>(
@@ -213,7 +215,7 @@ index fca86bd..3fb0f5e 100644
  
      // write the device file for the vlan interface.
      vlanIntf->writeDeviceFile();
-@@ -647,8 +708,6 @@ void EthernetInterface::writeConfigurationFile()
+@@ -780,8 +841,6 @@ void EthernetInterface::writeConfigurationFile()
      // write all the static ip address in the systemd-network conf file
  
      using namespace std::string_literals;
@@ -222,16 +224,12 @@ index fca86bd..3fb0f5e 100644
      namespace fs = std::experimental::filesystem;
  
      // if there is vlan interafce then write the configuration file
-@@ -717,42 +776,45 @@ void EthernetInterface::writeConfigurationFile()
+@@ -855,42 +914,45 @@ void EthernetInterface::writeConfigurationFile()
      }
  
      // Add the DHCP entry
 -    auto value = dHCPEnabled() ? "true"s : "false"s;
 -    stream << "DHCP="s + value + "\n";
--
--    // When the interface configured as dhcp, we don't need below given entries
--    // in config file.
--    if (dHCPEnabled() == false)
 +    std::string value = convertForMessage(EthernetInterfaceIntf::dHCPEnabled());
 +    std::string::size_type loc = value.rfind(".");
 +    std::string requestedDHCPState = value.substr(loc + 1);
@@ -242,14 +240,33 @@ index fca86bd..3fb0f5e 100644
 +    bool dhcpv4Requested = dhcpToBeEnabled(IP::Protocol::IPv4, mappedDHCPState);
 +    // Static IP addresses
 +    for (const auto& addr : addrs)
-     {
--        // Static
--        for (const auto& addr : addrs)
++    {
 +        bool isValidIPv4 = isValidIP(AF_INET, addr.second->address());
 +        bool isValidIPv6 = isValidIP(AF_INET6, addr.second->address());
 +        if (((!dhcpv4Requested && isValidIPv4) ||
 +             (!dhcpv6Requested && isValidIPv6)) &&
 +            addressIsStatic(addr.second->origin()))
++        {
++            // Process all static addresses
++            std::string address = addr.second->address() + "/" +
++                                  std::to_string(addr.second->prefixLength());
++
++            // build the address entries. Do not use [Network] shortcuts to
++            // insert address entries.
++            stream << "[Address]\n";
++            stream << "Address=" << address << "\n";
++        }
++    }
+ 
+-    // When the interface configured as dhcp, we don't need below given entries
+-    // in config file.
+-    if (dHCPEnabled() == false)
++    if (manager.getSystemConf())
+     {
+-        // Static
+-        for (const auto& addr : addrs)
++        const auto& gateway = manager.getSystemConf()->defaultGateway();
++        if (!gateway.empty())
          {
 -            if (addr.second->origin() == AddressOrigin::Static
 -#ifndef LINK_LOCAL_AUTOCONFIGURATION
@@ -263,22 +280,12 @@ index fca86bd..3fb0f5e 100644
 -
 -                stream << "Address=" << address << "\n";
 -            }
-+            // Process all static addresses
-+            std::string address = addr.second->address() + "/" +
-+                                  std::to_string(addr.second->prefixLength());
-+
-+            // build the address entries. Do not use [Network] shortcuts to
-+            // insert address entries.
-+            stream << "[Address]\n";
-+            stream << "Address=" << address << "\n";
++            stream << "Gateway=" << gateway << "\n";
          }
-+    }
- 
+-
 -        if (manager.getSystemConf())
-+    if (manager.getSystemConf())
-+    {
-+        const auto& gateway = manager.getSystemConf()->defaultGateway();
-+        if (!gateway.empty())
++        const auto& gateway6 = manager.getSystemConf()->defaultGateway6();
++        if (!gateway6.empty())
          {
 -            const auto& gateway = manager.getSystemConf()->defaultGateway();
 -            if (!gateway.empty())
@@ -290,16 +297,11 @@ index fca86bd..3fb0f5e 100644
 -            {
 -                stream << "Gateway=" << gateway6 << "\n";
 -            }
-+            stream << "Gateway=" << gateway << "\n";
-+        }
-+        const auto& gateway6 = manager.getSystemConf()->defaultGateway6();
-+        if (!gateway6.empty())
-+        {
 +            stream << "Gateway=" << gateway6 << "\n";
          }
      }
  
-@@ -863,7 +925,7 @@ std::string EthernetInterface::mACAddress(std::string value)
+@@ -1001,7 +1063,7 @@ std::string EthernetInterface::mACAddress(std::string value)
  
  void EthernetInterface::deleteAll()
  {
@@ -309,10 +311,10 @@ index fca86bd..3fb0f5e 100644
          log<level::INFO>("DHCP enabled on the interface"),
              entry("INTERFACE=%s", interfaceName().c_str());
 diff --git a/ethernet_interface.hpp b/ethernet_interface.hpp
-index 058d328..4e36ae8 100644
+index 6344533..3f7fd31 100644
 --- a/ethernet_interface.hpp
 +++ b/ethernet_interface.hpp
-@@ -92,7 +92,7 @@ class EthernetInterface : public Ifaces
+@@ -94,7 +94,7 @@ class EthernetInterface : public Ifaces
       *                          send.
       */
      EthernetInterface(sdbusplus::bus::bus& bus, const std::string& objPath,
@@ -320,8 +322,8 @@ index 058d328..4e36ae8 100644
 +                      DHCPConf dhcpEnabled, Manager& parent,
                        bool emitSignal = true);
  
-     /** @brief Function to create ipaddress dbus object.
-@@ -158,7 +158,34 @@ class EthernetInterface : public Ifaces
+     /** @brief Function used to load the nameservers.
+@@ -164,7 +164,34 @@ class EthernetInterface : public Ifaces
      }
  
      /** Set value of DHCPEnabled */
@@ -358,14 +360,14 @@ index 058d328..4e36ae8 100644
      /** Retrieve Link State */
      bool linkUp() const override;
 diff --git a/test/test_ethernet_interface.cpp b/test/test_ethernet_interface.cpp
-index 30dee8a..87fd68d 100644
+index d0beef7..3e2f9ff 100644
 --- a/test/test_ethernet_interface.cpp
 +++ b/test/test_ethernet_interface.cpp
-@@ -58,7 +58,8 @@ class TestEthernetInterface : public testing::Test
+@@ -59,7 +59,8 @@ class TestEthernetInterface : public testing::Test
      {
          mock_clear();
          mock_addIF("test0", 1, mac);
--        return {bus, "/xyz/openbmc_test/network/test0", false, manager};
+-        return {bus, "/xyz/openbmc_test/network/test0", false, manager, true};
 +        return {bus, "/xyz/openbmc_test/network/test0",
 +                EthernetInterface::DHCPConf::none, manager};
      }
@@ -500,5 +502,5 @@ index a994d05..37ae7ee 100644
      /** @brief Delete this d-bus object.
       */
 -- 
-2.25.1
+2.25.2
 
diff --git a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0011-Added-enable-disable-control-of-the-Network-Interfac.patch b/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0011-Added-enable-disable-control-of-the-Network-Interfac.patch
deleted file mode 100644
index 58dcf3f21..000000000
--- a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network/0011-Added-enable-disable-control-of-the-Network-Interfac.patch
+++ /dev/null
@@ -1,189 +0,0 @@
-From 4bfb4ad5ff795d78e06fbeaf1664df6819880f50 Mon Sep 17 00:00:00 2001
-From: Johnathan Mantey <johnathanx.mantey@intel.com>
-Date: Tue, 29 Oct 2019 16:20:28 -0700
-Subject: [PATCH] Added enable/disable control of the Network Interface Card
-
-Implemented enable/disable function to perform
-"ip link set eth(x) up"
-"ip link set eth(x) down"
-functionality from DBus.
-
-Tested:
-
-Confirmed Redfish PATCH commands on the InterfaceEnabled property
-changes the NIC state. Confirmed the NIC is DOWN/UP using "ip link".
-Confirmed "ip link" state changes can be obsserved from dbus-send
-commands, and from Redfish GET actions.
-
-Confirmed the link is inactive after a reboot.
-
-Confirmed link stays down despite assigning an IP manually.
-
-Confirmed link stays down despite enabling DHCP.
-
-Change-Id: I4152b53055e6546f7a6ca81b5a5eef6f689bcc66
-Signed-off-by: Johnathan Mantey <johnathanx.mantey@intel.com>
----
- ethernet_interface.cpp | 73 ++++++++++++++++++++++++++++++++++++++++--
- ethernet_interface.hpp | 11 ++++++-
- 2 files changed, 81 insertions(+), 3 deletions(-)
-
-diff --git a/ethernet_interface.cpp b/ethernet_interface.cpp
-index 8b8f698..a2754a4 100644
---- a/ethernet_interface.cpp
-+++ b/ethernet_interface.cpp
-@@ -85,6 +85,7 @@ EthernetInterface::EthernetInterface(sdbusplus::bus::bus& bus,
-     EthernetInterfaceIntf::autoNeg(std::get<2>(ifInfo));
-     EthernetInterfaceIntf::speed(std::get<0>(ifInfo));
-     EthernetInterfaceIntf::linkUp(std::get<3>(ifInfo));
-+    EthernetInterfaceIntf::nICEnabled(std::get<4>(ifInfo));
- #endif
-     getChannelPrivilege(intfName);
- 
-@@ -323,11 +324,12 @@ InterfaceInfo EthernetInterface::getInterfaceInfo() const
-     Autoneg autoneg{0};
-     DuplexMode duplex{0};
-     LinkUp linkState{false};
-+    NICEnabled nicEnabled{false};
-     EthernetIntfSocket eifSocket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
- 
-     if (eifSocket.sock < 0)
-     {
--        return std::make_tuple(speed, duplex, autoneg, linkState);
-+        return std::make_tuple(speed, duplex, autoneg, linkState, nicEnabled);
-     }
- 
-     std::strncpy(ifr.ifr_name, interfaceName().c_str(), IFNAMSIZ - 1);
-@@ -341,9 +343,10 @@ InterfaceInfo EthernetInterface::getInterfaceInfo() const
-         autoneg = edata.autoneg;
-     }
- 
-+    nicEnabled = nICEnabled();
-     linkState = linkUp();
- 
--    return std::make_tuple(speed, duplex, autoneg, linkState);
-+    return std::make_tuple(speed, duplex, autoneg, linkState, nicEnabled);
- }
- #endif
- 
-@@ -548,6 +551,67 @@ bool EthernetInterface::linkUp() const
-         log<level::ERR>("ioctl failed for SIOCGIFFLAGS:",
-                         entry("ERROR=%s", strerror(errno)));
-     }
-+    return value;
-+}
-+
-+bool EthernetInterface::nICEnabled() const
-+{
-+    EthernetIntfSocket eifSocket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
-+    bool value = EthernetInterfaceIntf::nICEnabled();
-+
-+    if (eifSocket.sock < 0)
-+    {
-+        return value;
-+    }
-+
-+    ifreq ifr{0};
-+    std::strncpy(ifr.ifr_name, interfaceName().c_str(), IF_NAMESIZE - 1);
-+    if (ioctl(eifSocket.sock, SIOCGIFFLAGS, &ifr) == 0)
-+    {
-+        value = static_cast<bool>(ifr.ifr_flags & IFF_UP);
-+    }
-+    else
-+    {
-+        log<level::ERR>("ioctl failed for SIOCGIFFLAGS:",
-+                        entry("ERROR=%s", strerror(errno)));
-+    }
-+    return value;
-+}
-+
-+bool EthernetInterface::nICEnabled(bool value)
-+{
-+    if (value == EthernetInterfaceIntf::nICEnabled())
-+    {
-+        return value;
-+    }
-+
-+    EthernetIntfSocket eifSocket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
-+    if (eifSocket.sock < 0)
-+    {
-+        return EthernetInterfaceIntf::nICEnabled();
-+    }
-+
-+    ifreq ifr{0};
-+    std::strncpy(ifr.ifr_name, interfaceName().c_str(), IF_NAMESIZE - 1);
-+    if (ioctl(eifSocket.sock, SIOCGIFFLAGS, &ifr) != 0)
-+    {
-+        log<level::ERR>("ioctl failed for SIOCGIFFLAGS:",
-+                        entry("ERROR=%s", strerror(errno)));
-+        return EthernetInterfaceIntf::nICEnabled();
-+    }
-+
-+    ifr.ifr_flags &= ~IFF_UP;
-+    ifr.ifr_flags |= value ? IFF_UP : 0;
-+
-+    if (ioctl(eifSocket.sock, SIOCSIFFLAGS, &ifr) != 0)
-+    {
-+        log<level::ERR>("ioctl failed for SIOCSIFFLAGS:",
-+                        entry("ERROR=%s", strerror(errno)));
-+        return EthernetInterfaceIntf::nICEnabled();
-+    }
-+    EthernetInterfaceIntf::nICEnabled(value);
-+    writeConfigurationFile();
-+    manager.restartSystemdUnit(networkdService);
- 
-     return value;
- }
-@@ -742,6 +806,11 @@ void EthernetInterface::writeConfigurationFile()
-         stream << "MACAddress=" << mac << "\n";
-     }
- 
-+    if (!nICEnabled())
-+    {
-+        stream << "Unmanaged=yes\n";
-+    }
-+
-     // write the network section
-     stream << "[Network]\n";
- #ifdef LINK_LOCAL_AUTOCONFIGURATION
-diff --git a/ethernet_interface.hpp b/ethernet_interface.hpp
-index 4e36ae8..104750e 100644
---- a/ethernet_interface.hpp
-+++ b/ethernet_interface.hpp
-@@ -60,9 +60,11 @@ using LinkSpeed = uint16_t;
- using DuplexMode = uint8_t;
- using Autoneg = uint8_t;
- using LinkUp = bool;
-+using NICEnabled = bool;
- using VlanId = uint32_t;
- using InterfaceName = std::string;
--using InterfaceInfo = std::tuple<LinkSpeed, DuplexMode, Autoneg, LinkUp>;
-+using InterfaceInfo =
-+    std::tuple<LinkSpeed, DuplexMode, Autoneg, LinkUp, NICEnabled>;
- using AddressMap = std::map<std::string, std::shared_ptr<IPAddress>>;
- using NeighborMap = std::map<std::string, std::shared_ptr<Neighbor>>;
- using VlanInterfaceMap =
-@@ -190,6 +192,12 @@ class EthernetInterface : public Ifaces
-     /** Retrieve Link State */
-     bool linkUp() const override;
- 
-+    /** Retrieve NIC State */
-+    bool nICEnabled() const override;
-+
-+    /** Set value of NICEnabled */
-+    bool nICEnabled(bool value) override;
-+
-     /** @brief sets the MAC address.
-      *  @param[in] value - MAC address which needs to be set on the system.
-      *  @returns macAddress of the interface or throws an error.
-@@ -246,6 +254,7 @@ class EthernetInterface : public Ifaces
-     using EthernetInterfaceIntf::dHCPEnabled;
-     using EthernetInterfaceIntf::interfaceName;
-     using EthernetInterfaceIntf::linkUp;
-+    using EthernetInterfaceIntf::nICEnabled;
-     using MacAddressIntf::mACAddress;
- 
-     /** @brief Absolute path of the resolv conf file */
--- 
-2.24.1
-
diff --git a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network_%.bbappend b/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network_%.bbappend
index fe7f050c0..5774d5318 100644
--- a/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-network/network/phosphor-network_%.bbappend
@@ -6,8 +6,7 @@ DEPENDS += "nlohmann-json boost"
 SRC_URI = "git://github.com/openbmc/phosphor-networkd;nobranch=1"
 SRC_URI += "file://0003-Adding-channel-specific-privilege-to-network.patch \
             file://0009-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-enabled.patch \
-            file://0011-Added-enable-disable-control-of-the-Network-Interfac.patch \
             "
-SRCREV = "ad4bf5ce1292c74ac2ecea413ff27c14cf5748fe"
+SRCREV = "d0679f9bb46670c593061c4aaebec2a577cdd5c3"
 
 EXTRA_OECONF_append = " --enable-nic-ethtool=yes"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/configuration/entity-manager_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/configuration/entity-manager_%.bbappend
index 59330e8f3..01c9ead9f 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/configuration/entity-manager_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/configuration/entity-manager_%.bbappend
@@ -1,6 +1,6 @@
 # this is here just to bump faster than upstream
 SRC_URI = "git://github.com/openbmc/entity-manager.git"
-SRCREV = "ff58eba9e7f06b60879db38e1be6b41c6b2b9092"
+SRCREV = "2539ccd113174d37feb1b0c036f97ada68f541e7"
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0028-MCTP-Daemon-D-Bus-interface-definition.patch b/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0028-MCTP-Daemon-D-Bus-interface-definition.patch
new file mode 100644
index 000000000..fba025207
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0028-MCTP-Daemon-D-Bus-interface-definition.patch
@@ -0,0 +1,459 @@
+From 7a3fc3a969d2a187be20a972a5a7209944731bea Mon Sep 17 00:00:00 2001
+From: "Kowalski, Mariusz" <mariusz.kowalski@intel.com>
+Date: Thu, 27 Feb 2020 15:48:56 +0100
+Subject: [PATCH] MCTP Daemon D-Bus interface definition.
+
+This interface definition was created on base of the MCTP design
+proposed in this document:
+https://gerrit.openbmc-project.xyz/c/openbmc/docs/+/28424/9/designs/mctp.md
+
+Signed-off-by: Mariusz Kowalski <mariusz.kowalski@intel.com>
+Signed-off-by: Karol Wachowski <karol.wachowski@intel.com>
+Change-Id: Ida66f8ffcf00003655edcb0fb0112202797b8e1a
+---
+ xyz/openbmc_project/MCTP/Base.interface.yaml  | 231 ++++++++++++++++++
+ .../MCTP/Binding/PCIe.interface.yaml          |  29 +++
+ .../MCTP/Binding/SMBus.interface.yaml         |  17 ++
+ .../MCTP/BusOwner.interface.yaml              |  15 ++
+ .../MCTP/Endpoint.interface.yaml              |  19 ++
+ xyz/openbmc_project/MCTP/README.md            |  38 +++
+ .../MCTP/SupportedMessageTypes.interface.yaml |  36 +++
+ 7 files changed, 385 insertions(+)
+ create mode 100644 xyz/openbmc_project/MCTP/Base.interface.yaml
+ create mode 100644 xyz/openbmc_project/MCTP/Binding/PCIe.interface.yaml
+ create mode 100644 xyz/openbmc_project/MCTP/Binding/SMBus.interface.yaml
+ create mode 100644 xyz/openbmc_project/MCTP/BusOwner.interface.yaml
+ create mode 100644 xyz/openbmc_project/MCTP/Endpoint.interface.yaml
+ create mode 100644 xyz/openbmc_project/MCTP/README.md
+ create mode 100644 xyz/openbmc_project/MCTP/SupportedMessageTypes.interface.yaml
+
+diff --git a/xyz/openbmc_project/MCTP/Base.interface.yaml b/xyz/openbmc_project/MCTP/Base.interface.yaml
+new file mode 100644
+index 0000000..9a649a5
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/Base.interface.yaml
+@@ -0,0 +1,231 @@
++description: >
++  Mandatory interface for each instance of the MCTP Daemon to expose
++  the base MCTP daemon and medium type interfaces.
++
++methods:
++    - name: SendMctpMessagePayload
++      description: >
++        Sends message over MCTP interface
++      parameters:
++        - name: DestinationEID
++          type: byte
++          description: >
++            Destination Endpoint ID. The logical address used to route MCTP
++            messages to a specific MCTP endpoint.
++        - name: MsgTag
++          type: byte
++          description: >
++            Message tag. Field that, along with the Source Endpoint IDs and the
++            Tag Owner (TO) field, identifies a unique message at the MCTP
++            transport level.
++        - name: TagOwner
++          type: boolean
++          description: >
++            Tag Owner bit identifies whether the message tag was originated by
++            the endpoint that is the source of the message or by the endpoint
++            that is the destination of the message.
++        - name: Payload
++          type: array[byte]
++          description: Payload of message.
++      returns:
++        - name: Status
++          type: byte
++          description: 0 - if success
++      errors:
++        - xyz.openbmc_project.Common.Error.Timeout
++        - xyz.openbmc_project.Common.Error.InvalidArgument
++        - xyz.openbmc_project.Common.Error.InternalFailure
++
++    - name: SendMctpMessageFileDescriptor
++      description: >
++        Sends message over MCTP interface
++      parameters:
++        - name: DestinationEID
++          type: byte
++          description: >
++            Destination Endpoint ID. The logical address used to route MCTP
++            messages to a specific MCTP endpoint.
++        - name: MsgTag
++          type: byte
++          description: >
++            Message tag. Field that, along with the Source Endpoint IDs and the
++            Tag Owner (TO) field, identifies a unique message at the MCTP
++            transport level.
++        - name: TagOwner
++          type: boolean
++          description: >
++            Tag Owner bit identifies whether the message tag was originated by
++            the endpoint that is the source of the message or by the endpoint
++            that is the destination of the message.
++        - name: FileDescriptor
++          type: unixfd
++          description: File descriptor of message.
++      returns:
++        - name: Status
++          type: byte
++          description: 0 - if success
++      errors:
++        - xyz.openbmc_project.Common.Error.Timeout
++        - xyz.openbmc_project.Common.Error.InvalidArgument
++        - xyz.openbmc_project.Common.Error.InternalFailure
++
++signals:
++    - name: MessageReceivedSignal
++      description: >
++        Signal indicating upper layers about arrival of a MCTP message.
++      properties:
++        - name: MessageType
++          type: enum[self.MessageTypes]
++          description: >
++            Defines the values for the Message Type field for different message
++            types transported through MCTP.
++        - name: SrcEid
++          type: byte
++          description: >
++            Source Endpoint ID. The logical address used to route MCTP messages
++            to a specific MCTP endpoint.
++        - name: MsgTag
++          type: byte
++          description: >
++            Message tag. Field that, along with the Source Endpoint IDs and the
++            Tag Owner (TO) field, identifies a unique message at the MCTP
++            transport level.
++        - name: TagOwner
++          type: boolean
++          description: >
++            Tag Owner bit identifies whether the message tag was originated by
++            the endpoint that is the source of the message or by the endpoint
++            that is the destination of the message.
++        - name: Payload
++          type: array[byte]
++          description: Payload of message.
++
++properties:
++    - name: Eid
++      type: byte
++      description: >
++        Endpoint ID. The logical address used to route MCTP messages to a
++        specific MCTP endpoint.
++
++    - name: BindingID
++      type: enum[self.BindingTypes]
++
++    - name: BindingMediumID
++      type: enum[self.MctpPhysicalMediumIdentifiers]
++
++    - name: StaticEid
++      type: boolean
++      description: Support for statically/dynamicly allocated IDs
++
++    - name: Uuid
++      type: array[byte]
++      description: Guid - 16bytes
++
++    - name: BindingMode
++      type: enum[self.BindingModeTypes]
++      description: Bus Owner / Endpoint / Bridge
++
++enumerations:
++  - name: BindingTypes
++    description: >
++      All other values than described are reserved.
++    values:
++      - name: MctpOverSmbus
++      - name: MctpOverPcieVdm
++      - name: MctpOverUsb
++        description: Reserved for MCTP over USB
++      - name: MctpOverKcs
++      - name: MctpOverSerial
++      - name: VendorDefined
++
++  - name: MctpPhysicalMediumIdentifiers
++    description: >
++      Identifies MCTP physical medium identifiers. see DSP0239.
++    values:
++        - name: Smbus
++          descritpion: SMBus 2.0 100 kHz compatible
++        - name: SmbusI2c
++          descritpion: SMBus 2.0 + I2C 100 kHz compatible
++        - name: I2cCompatible
++          description: I2C 100 kHz compatible (Standard-mode)
++        - name: Smbus3OrI2c400khzCompatible
++          description: SMBus 3.0 or I2C 400 kHz compatible (Fast-mode)
++        - name: Smbus3OrI2c1MhzCompatible
++          description: SMBus 3.0 or I2C 1 MHz compatible (Fast-mode Plus)
++        - name: I2c3Mhz4Compatible
++          description: I2C 3.4 MHz compatible (High-speed mode)
++        - name: Pcie11
++          description: PCIe revision 1.1 compatible
++        - name: Pcie2
++          description: PCIe revision 2.0 compatible
++        - name: Pcie21
++          description: PCIe revision 2.1 compatible
++        - name: Pcie3
++          description: PCIe revision 3.0 compatible
++        - name: Pcie4
++          description: PCIe revision 4.0 compatible
++        - name: Pcie5
++          description: PCIe revision 4.0 compatible
++        - name:  PciCompatible
++          description: >
++            PCI compatible (PCI 1.0,2.0,2.1,2.2,2.3,3.0,PCI-X 1.0, PCI-X 2.0)
++        - name: Usb11Compatible
++          description: USB 1.1 compatible
++        - name: Usb20Compatible
++          description: USB 2.0 compatible
++        - name: Usb30Compatible
++          description: USB 3.0 compatible
++        - name: NcSiOverRbt
++          description: >
++            NC-SI over RBT (A physical interface based on RMII as defined in
++            DSP0222)
++        - name: KcsLegacy
++          description: KCS1 / Legacy (Fixed Address Decoding)
++        - name: KcsPci
++          description: KCS1 / PCI (Base Class 0xC0 Subclass 0x01)
++        - name: SerialHostLegacy
++          description: Serial Host2 / Legacy (Fixed Address Decoding)
++        - name: SerialHostPci
++          description: Serial Host2 / PCI (Base Class 0x07 Subclass 0x00)
++        - name: AsynchronousSerial
++          description: Asynchronous Serial (Between MCs and IMDs)
++        - name: I3cSDR
++          description: I3C 12.5 MHz compatible (SDR)
++        - name: I3cHDRDDR
++          description: I3C 25 MHz compatible (HDR-DDR)
++
++  - name: BindingModeTypes
++    values:
++        - name: Endpoint
++          description: >
++            An MCTP communication terminus. An MCTP endpoint is a terminus or
++            origin of MCTP packets or messages. That is, the combined
++            functionality within a physical device that communicates using the
++            MCTP transport protocol and handles MCTP control commands. This
++            includes MCTP-capable management controllers and managed devices.
++            Also referred to in this document as "endpoint".
++        - name: BusOwner
++          description: >
++            The party responsible for managing address assignments (can be
++            logical or physical addresses) on a bus (for example, in MCTP, the
++            bus owner is the party responsible for managing EID assignments for
++            a given bus). A bus owner may also have additional media-specific
++            responsibilities, such as assignment of physical addresses.
++        - name: Bridge
++          description: >
++            An MCTP endpoint that can route MCTP messages not destined for
++            itself that it receives on one interconnect onto another without
++            interpreting them. The ingress and egress media at the bridge may
++            be either homogeneous or heterogeneous. Also referred to in this
++            document as a "bridge".
++
++  - name: MessageTypes
++    values:
++    - name: MctpControl
++    - name: PLDM
++    - name: NCSI
++    - name: Ethernet
++    - name: NVMeMgmtMsg
++    - name: SPDM
++    - name: VDPCI
++    - name: VDIANA
+diff --git a/xyz/openbmc_project/MCTP/Binding/PCIe.interface.yaml b/xyz/openbmc_project/MCTP/Binding/PCIe.interface.yaml
+new file mode 100644
+index 0000000..1bd2881
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/Binding/PCIe.interface.yaml
+@@ -0,0 +1,29 @@
++description: >
++    Interface exposed by MCTP daemon for PCIe binding
++
++properties:
++    - name: DiscoveredFlag
++      type: enum[self.DiscoveryFlags]
++      description: >
++        Each endpoint (except the bus owner) on the PCIe bus maintains an
++        internal flag called the Discovered flag. The flag is set to the
++        discovered state when the Set Endpoint ID command is received.
++
++    - name: BDF
++      type: uint16
++      description: >
++        Byte 1 [7:0] Bus number
++        Byte 2 [7:3] Device number [2:0] Function Number
++
++enumerations:
++    - name: DiscoveryFlags
++      description: >
++          The Prepare for Endpoint Discovery message causes each recipient
++          endpoint on the PCIe bus to set their respective Discovered flag to
++          the undiscovered state. For the Prepare for Endpoint Discovery request
++          message, the routing in the physical transport header should be set to
++          011b (Broadcast from Root Complex).
++      values:
++        - name: Discovered
++        - name: Undiscovered
++        - name: NotApplicable
+diff --git a/xyz/openbmc_project/MCTP/Binding/SMBus.interface.yaml b/xyz/openbmc_project/MCTP/Binding/SMBus.interface.yaml
+new file mode 100644
+index 0000000..9219ad0
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/Binding/SMBus.interface.yaml
+@@ -0,0 +1,17 @@
++description: >
++  Interface exposed by MCTP daemon for SMBus binding
++
++properties:
++    - name: ArpMasterSupport
++      type: boolean
++      description: >
++        The SMBus binding can also run ARP Master protocol and
++        assign SMBus addresses to the devices on the bus.
++
++    - name: BusNumber
++      type: byte
++      description: I2C bus number of the medium used
++
++    - name: SlaveAddress
++      type: byte
++      description: Slave address to be used for this medium
+diff --git a/xyz/openbmc_project/MCTP/BusOwner.interface.yaml b/xyz/openbmc_project/MCTP/BusOwner.interface.yaml
+new file mode 100644
+index 0000000..0853381
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/BusOwner.interface.yaml
+@@ -0,0 +1,15 @@
++description: >
++    Interface exposed by MCTP root object, when executing in Bus Owner mode.
++
++properties:
++    - name: EidPool
++      type: array[struct[byte, byte]]
++      description: Pool of allowed EIDs to be used
++
++    - name: TopMostBusOwner
++      type: boolean
++      description: To indicate whether BMC is topmost Bus Owner
++
++    - name: OwnEidPool
++      type: boolean
++      description: Indicates Eid pool is managed by self
+diff --git a/xyz/openbmc_project/MCTP/Endpoint.interface.yaml b/xyz/openbmc_project/MCTP/Endpoint.interface.yaml
+new file mode 100644
+index 0000000..b7f9a67
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/Endpoint.interface.yaml
+@@ -0,0 +1,19 @@
++description:
++  Interface exposed by discovered MCTP endpoints.
++
++properties:
++    - name: Uuid
++      type: array[byte]
++      description: >
++        Universally unique identifier (UUID), also referred to as a globally
++        unique ID (GUID), for the management controller or management device.
++
++    - name: Mode
++      type: enum[xyz.openbmc_project.MCTP.Base.BindingModeTypes]
++      description: Endpoint / BusOwner / Bridge
++
++    - name: NetworkId
++      type: uint16
++      description: >
++        MCTP network ID a unique identifier to distinguish each independent
++        MCTP network within a platform.
+diff --git a/xyz/openbmc_project/MCTP/README.md b/xyz/openbmc_project/MCTP/README.md
+new file mode 100644
+index 0000000..1c3b4aa
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/README.md
+@@ -0,0 +1,38 @@
++# MCTP Daemon
++
++## Overview
++MCTP service exposes D-Bus methods / properties / signals for managing
++MCTP devices or work as MCTP Endpoint. MCTP daemon will either
++work in Bus Owner or Endpoint mode for the specified physical medium.
++
++### MCTP service
++MCTP service can be started either in Bus Owner mode or Endpoint mode.
++It will expose following objects.
++1. Base object
++2. MCTP Endpoints (discovered in case of Bus Owner mode, queried using
++routing table in case of Endpoint mode)
++Please refer individual yaml file for details about the
++methods / signals / properties exposed in the interfaces.
++
++#### Base object
++Exposed under the path `/xyz/openbmc_project/mctp` with the following
++interfaces.
++1. `xyz.openbmc_project.MCTP.Base` which exposes all the common properties
++needed for MCTP Daemon.
++2. `xyz.openbmc_project.MCTP.BusOwner` available only in Bus Owner mode
++which exposes the properties needed by Bus Owner MCTP Daemon.
++3. `xyz.openbmc_project.MCTP.SupportedMessageTypes` which exposes the message
++types supported.
++4. Binding interface `xyz.openbmc_project.MCTP.Binding.PCIe` or
++`xyz.openbmc_project.MCTP.Binding.SMBus` as per the physical medium in which
++this MCTP Daemon is instantiated.
++
++#### Endpoint object
++Exposed under the path `/xyz/openbmc_project/mctp/device/<eid>` with the
++following interfaces.
++1. `xyz.openbmc_project.MCTP.SupportedMessageTypes` which exposes supported MCTP
++message types for the discovered MCTP Endpoint.
++2. `xyz.openbmc_project.MCTP.Enpoint` which exposes properties like UUID and endpoint
++mode (to identify Bus Owner or Bridge or Endpoint) for the discovered MCTP Endpoint.
++3. `xyz.openbmc_project.MCTP.Bridge` available only for discovered MCTP Bridges to
++expose properties like EID pool. (TBD)
+diff --git a/xyz/openbmc_project/MCTP/SupportedMessageTypes.interface.yaml b/xyz/openbmc_project/MCTP/SupportedMessageTypes.interface.yaml
+new file mode 100644
+index 0000000..fa447ee
+--- /dev/null
++++ b/xyz/openbmc_project/MCTP/SupportedMessageTypes.interface.yaml
+@@ -0,0 +1,36 @@
++description:
++  Interface used to represent the supported MCTP message types.
++  This will be exposed by all MCTP endpoints.
++
++properties:
++    - name: MctpControl
++      type: boolean
++      description: Indicates support availability
++
++    - name: PLDM
++      type: boolean
++      description: Indicates support availability
++
++    - name: NCSI
++      type: boolean
++      description: Indicates support availability
++
++    - name: Ethernet
++      type: boolean
++      description: Indicates support availability
++
++    - name: NVMeMgmtMsg
++      type: boolean
++      description: Indicates support availability
++
++    - name: SPDM
++      type: boolean
++      description: Indicates support availability
++
++    - name: VDPCI
++      type: boolean
++      description: Indicates support availability
++
++    - name: VDIANA
++      type: boolean
++      description: Indicates support availability
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend
index 63124074a..91f3d8311 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend
@@ -12,4 +12,5 @@ SRC_URI += "file://0005-Add-DBUS-interface-of-CPU-and-Memory-s-properties.patch
             file://0025-Add-PreInterruptFlag-properity-in-DBUS.patch \
             file://0001-Reapply-Enhance-DHCP-beyond-just-OFF-and-IPv4-IPv6-e.patch \
             file://0026-Add-StandbySpare-support-for-software-inventory.patch \
+            file://0028-MCTP-Daemon-D-Bus-interface-definition.patch \
             "
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager/0008-item_updater-update-the-bmc_active-objectPath.patch b/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager/0008-item_updater-update-the-bmc_active-objectPath.patch
new file mode 100644
index 000000000..bac756a18
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager/0008-item_updater-update-the-bmc_active-objectPath.patch
@@ -0,0 +1,30 @@
+From d9e50ecf8bd8bc764838e7244084184644a3f0fc Mon Sep 17 00:00:00 2001
+From: Chalapathi <chalapathix.venkataramashetty@intel.com>
+Date: Thu, 23 Apr 2020 19:06:19 +0000
+Subject: [PATCH] item_updater: update the bmc_active objectPath
+
+Update the Software object path to bmc_active instead of random Id.
+
+Signed-off-by: Chalapathi <chalapathix.venkataramashetty@intel.com>
+---
+ item_updater.cpp | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/item_updater.cpp b/item_updater.cpp
+index 7fe69e4..3ce1dbf 100644
+--- a/item_updater.cpp
++++ b/item_updater.cpp
+@@ -175,9 +175,7 @@ void ItemUpdater::processBMCImage()
+         if (0 ==
+             iter.path().native().compare(0, BMC_RO_PREFIX_LEN, BMC_ROFS_PREFIX))
+         {
+-            // The versionId is extracted from the path
+-            // for example /media/ro-2a1022fe.
+-            auto id = iter.path().native().substr(BMC_RO_PREFIX_LEN);
++            std::string id = "bmc_active";
+             auto osRelease = iter.path() / OS_RELEASE_FILE;
+             if (!fs::is_regular_file(osRelease))
+             {
+-- 
+2.17.1
+
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager_%.bbappend
index 96ddfc3ca..edd4254ce 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/flash/phosphor-software-manager_%.bbappend
@@ -10,6 +10,7 @@ SRC_URI += "file://0002-Redfish-firmware-activation.patch \
             file://0005-Modified-firmware-activation-to-launch-fwupd.sh-thro.patch \
             file://0006-Modify-the-ID-of-software-image-updater-object-on-DB.patch \
             file://0007-Adding-StandBySpare-for-firmware-activation.patch \
+            file://0008-item_updater-update-the-bmc_active-objectPath.patch \
            "
 
 SRC_URI_PFR = "file://0007-PFR-images-support.patch \
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/fru/default-fru/checkFru.sh b/meta-openbmc-mods/meta-common/recipes-phosphor/fru/default-fru/checkFru.sh
index 52da21230..9227beb20 100755
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/fru/default-fru/checkFru.sh
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/fru/default-fru/checkFru.sh
@@ -29,12 +29,12 @@ if grep -q 'CPU part\s*: 0xb76' /proc/cpuinfo; then
     case $BOARD_ID in
         12) NAME="D50TNP1SB"
             PRODID="0x99";;
-        38) NAME="WilsonCity"
-            PRODID="0x91";;
         40) NAME="CooperCity"
             PRODID="0x9d";;
         42) NAME="WilsonCity"
             PRODID="0x91";;
+        44) NAME="WilsonCityM"
+            PRODID="0x91";;
         45) NAME="WilsonCity"
             PRODID="0x91";;
         60) NAME="M50CYP2SB2U"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb/0002-Use-chip-id-based-UUID-for-Service-Root.patch b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb/0002-Use-chip-id-based-UUID-for-Service-Root.patch
new file mode 100644
index 000000000..03c27fb43
--- /dev/null
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb/0002-Use-chip-id-based-UUID-for-Service-Root.patch
@@ -0,0 +1,71 @@
+From d629bf86a9ac970d8c0505c0aa2488373c9df102 Mon Sep 17 00:00:00 2001
+From: Wiktor Golgowski <wiktor.golgowski@linux.intel.com>
+Date: Thu, 30 Apr 2020 11:09:35 +0200
+Subject: [PATCH] Use chip id-based UUID for Service Root.
+
+If the sysfs-provided chip id is available, it will be used as
+payload to generate Service Root UUID from hardcoded namespace.
+
+Tested:
+Generated UUID is consistent between BMC image reflashes.
+If the sysfs node is not available, code falls back to randomly
+generated UUID.
+
+Signed-off-by: Wiktor Gołgowski <wiktor.golgowski@linux.intel.com>
+---
+ include/persistent_data_middleware.hpp | 32 +++++++++++++++++++++++---
+ 1 file changed, 29 insertions(+), 3 deletions(-)
+
+diff --git a/include/persistent_data_middleware.hpp b/include/persistent_data_middleware.hpp
+index 348079b..925e7b6 100644
+--- a/include/persistent_data_middleware.hpp
++++ b/include/persistent_data_middleware.hpp
+@@ -30,6 +30,10 @@ class Middleware
+   public:
+     // todo(ed) should read this from a fixed location somewhere, not CWD
+     static constexpr const char* filename = "bmcweb_persistent_data.json";
++    static constexpr const char* chipIdSysfsNode = "/sys/devices/platform"
++    "/ahb/ahb:apb/1e6e2000.syscon/1e6e2000.syscon:misc_control/chip_id";
++    static constexpr const char* UuidNs = "{b7b0553a-54cc-4162-982d-"
++    "944847ed76f5}";
+ 
+     struct Context
+     {
+@@ -143,9 +147,31 @@ class Middleware
+ 
+         if (systemUuid.empty())
+         {
+-            systemUuid =
+-                boost::uuids::to_string(boost::uuids::random_generator()());
+-            needWrite = true;
++            // Try to retrieve chip id-based uuid.
++            std::ifstream chipIdFile(chipIdSysfsNode);
++            if (chipIdFile.is_open())
++            {
++                std::string chipId;
++                std::getline(chipIdFile, chipId);
++                if (!chipId.empty())
++                {
++                    boost::uuids::name_generator_sha1 gen(
++                        boost::uuids::string_generator()(UuidNs));
++                    systemUuid = boost::uuids::to_string(gen(chipId.c_str()));
++                    needWrite = true;
++                }
++                else
++                {
++                    BMCWEB_LOG_ERROR << "Cannot get chip id-based System UUID.";
++                }
++            }
++            // If the above fails, generate random uuid.
++            if (systemUuid.empty())
++            {
++                systemUuid =
++                    boost::uuids::to_string(boost::uuids::random_generator()());
++                needWrite = true;
++            }
+         }
+         if (fileRevision < jsonRevision)
+         {
+-- 
+2.20.1
+
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
index 2e59a7b78..c9f95121f 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend
@@ -1,6 +1,6 @@
 # todo(james) remove nobranch
 SRC_URI = "git://github.com/openbmc/bmcweb.git"
-SRCREV = "e5aaf047b6b41b0837ef0846cf5356c9a6bcb030"
+SRCREV = "8a3bb71ebcdf14dafd5967192f73bf2416e8bb6e"
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 
@@ -11,6 +11,7 @@ USERADD_PARAM_${PN} = "-r -s /usr/sbin/nologin -d /home/bmcweb -m -G shadow bmcw
 GROUPADD_PARAM_${PN} = "web; redfish "
 
 SRC_URI += "file://0001-Firmware-update-support-for-StandBySpare.patch \
+            file://0002-Use-chip-id-based-UUID-for-Service-Root.patch \
 "
 
 # Enable PFR support
@@ -19,9 +20,6 @@ EXTRA_OECMAKE += "${@bb.utils.contains('IMAGE_FSTYPES', 'intel-pfr', '-DBMCWEB_E
 # Enable NBD_PROXY
 EXTRA_OECMAKE += " -DBMCWEB_ENABLE_VM_NBDPROXY=ON"
 
-# Disable MTLS until it passes security review
-EXTRA_OECMAKE += " -DBMCWEB_ENABLE_MUTUAL_TLS_AUTHENTICATION=OFF"
-
 # Enable Validation unsecure based on IMAGE_FEATURES
 EXTRA_OECMAKE += "${@bb.utils.contains('EXTRA_IMAGE_FEATURES', 'validation-unsecure', '-DBMCWEB_ENABLE_VALIDATION_UNSECURE_FEATURE=ON', '', d)}"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-kcs_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-kcs_%.bbappend
index adb1cc551..97d329498 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-kcs_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-kcs_%.bbappend
@@ -11,7 +11,7 @@ SMM_DEVICE = "ipmi_kcs4"
 SYSTEMD_SERVICE_${PN}_append = " ${PN}@${SMM_DEVICE}.service "
 
 SRC_URI = "git://github.com/openbmc/kcsbridge.git"
-SRCREV = "46525ae48db23333493ac927c12ed13a0e663de5"
+SRCREV = "58d596ad9625790b5e06804360aa161579364425"
 
 SRC_URI += "file://99-ipmi-kcs.rules"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-net_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-net_%.bbappend
index 6ea4aa960..15a0041c2 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-net_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/ipmi/phosphor-ipmi-net_%.bbappend
@@ -3,7 +3,7 @@ inherit useradd
 # TODO: This should be removed, once up-stream bump up
 # issue is resolved
 SRC_URI += "git://github.com/openbmc/phosphor-net-ipmid"
-SRCREV = "9979e9971e17c974f29ec9ab720f5482308c119c"
+SRCREV = "a6ad5e161e5e5db4258b04254b19796f154b8533"
 
 USERADD_PACKAGES = "${PN}"
 # add a group called ipmi
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/libmctp-intel_git.bb b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/libmctp-intel_git.bb
index f7bec2af9..82305938d 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/libmctp-intel_git.bb
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/libmctp-intel_git.bb
@@ -2,7 +2,7 @@ SUMMARY = "libmctp_intel"
 DESCRIPTION = "Implementation of MCTP(DMTF DSP0236)"
 
 SRC_URI = "git://github.com/Intel-BMC/libmctp.git;protocol=ssh"
-SRCREV = "9f0aa081fdcc1ad5a8ca9025dbd0a559a68f4005"
+SRCREV = "a077c8ca846574509983d10aaa33de943ab6388a"
 
 S = "${WORKDIR}/git/"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb
index d9a2297ac..d0a03636d 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/pmci/mctpd.bb
@@ -5,7 +5,7 @@ LICENSE = "Apache-2.0"
 LIC_FILES_CHKSUM = "file://LICENSE;md5=e3fc50a88d0a364313df4b21ef20c29e"
 
 SRC_URI = "git://github.com/Intel-BMC/pmci.git;protocol=ssh"
-SRCREV = "34e98dc5e6bac78ccee86fb1ea1837b9ef1360a5"
+SRCREV = "626ae6b67b1e2c53e25c0be0b42561c6776be1c7"
 
 S = "${WORKDIR}/git/mctpd/"
 
@@ -25,8 +25,10 @@ DEPENDS += " \
     cli11 \
     nlohmann-json \
     gtest \
+    phosphor-dbus-interfaces \
     "
 SMBUS_BINDING = "smbus"
 
 FILES_${PN} += "${systemd_system_unitdir}/xyz.openbmc_project.mctpd@.service"
 SYSTEMD_SERVICE_${PN} += "xyz.openbmc_project.mctpd@${SMBUS_BINDING}.service"
+FILES_${PN} += "/usr/share/mctp/mctp_config.json"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
index f8ca43c3c..69b721779 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/sensors/dbus-sensors_%.bbappend
@@ -1,5 +1,5 @@
-SRCREV = "17aba776373e14851a04e6b9ac518622b117b2a1"
-SRC_URI = "git://github.com/openbmc/dbus-sensors.git"
+SRCREV = "10306bd5032fda014628487665d8000c0db49177"
+#SRC_URI = "git://github.com/openbmc/dbus-sensors.git"
 
 DEPENDS_append = " libgpiod libmctp"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/virtual-media/virtual-media.bb b/meta-openbmc-mods/meta-common/recipes-phosphor/virtual-media/virtual-media.bb
index 5b74dec5e..333611dbb 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/virtual-media/virtual-media.bb
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/virtual-media/virtual-media.bb
@@ -14,11 +14,12 @@ SYSTEMD_SERVICE_${PN} += "xyz.openbmc_project.VirtualMedia.service"
 
 DEPENDS = "udev boost nlohmann-json systemd sdbusplus"
 
-# Temporarily not needed due to Legacy mode disabling
-# RDEPENDS_${PN} = "nbdkit"
+# Needed for legacy mode
+RDEPENDS_${PN} = "nbdkit"
 
 inherit cmake systemd
 
 EXTRA_OECMAKE += "-DYOCTO_DEPENDENCIES=ON"
+EXTRA_OECMAKE += "-DLEGACY_MODE_ENABLED=ON"
 
 FULL_OPTIMIZATION = "-Os -pipe -flto -fno-rtti"
diff --git a/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend b/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
index 5923eb8d9..2382b20e7 100644
--- a/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-phosphor/webui/phosphor-webui_%.bbappend
@@ -1,4 +1,4 @@
 SRC_URI = "git://github.com/Intel-BMC/phosphor-webui;protocol=ssh;branch=intel2"
 FILESEXTRAPATHS_prepend_intel := "${THISDIR}/${PN}:"
 
-SRCREV = "8dea5a0000fcf9d1daada0b92811d9f1bf308a9f"
+SRCREV = "3d8dcffe2bbbdbb0212507bec60eb4e9f91c1d18"
diff --git a/meta-openbmc-mods/meta-common/recipes-utilities/nbdkit/nbdkit_git.bb b/meta-openbmc-mods/meta-common/recipes-utilities/nbdkit/nbdkit_git.bb
index d74c13427..207a8ede3 100644
--- a/meta-openbmc-mods/meta-common/recipes-utilities/nbdkit/nbdkit_git.bb
+++ b/meta-openbmc-mods/meta-common/recipes-utilities/nbdkit/nbdkit_git.bb
@@ -13,7 +13,7 @@ SRC_URI = "git://github.com/libguestfs/nbdkit.git;protocol=https"
 SRC_URI += "file://0001-Force-nbdkit-to-send-PATCH-as-upload-method.patch"
 
 PV = "1.17.5+git${SRCPV}"
-SRCREV = "0a76cae407aca6411af3c7db1efafc56dcd151ed"
+SRCREV = "c8406880c6603bb617dae131dd0a8826c05869ca"
 
 S = "${WORKDIR}/git"
 
diff --git a/meta-openbmc-mods/meta-common/recipes-x86/chassis/x86-power-control_%.bbappend b/meta-openbmc-mods/meta-common/recipes-x86/chassis/x86-power-control_%.bbappend
index 9323dc003..600f9e25f 100755
--- a/meta-openbmc-mods/meta-common/recipes-x86/chassis/x86-power-control_%.bbappend
+++ b/meta-openbmc-mods/meta-common/recipes-x86/chassis/x86-power-control_%.bbappend
@@ -1,3 +1,3 @@
 # Enable downstream autobump
 SRC_URI = "git://github.com/openbmc/x86-power-control.git;protocol=ssh"
-SRCREV = "fc1ecc59100d21c953501703bc5db9e02e25b333"
+SRCREV = "35aa665e01cf9d735ba4aeb3818a60caab376692"
diff --git a/meta-openbmc-mods/meta-egs/conf/bblayers.conf.sample b/meta-openbmc-mods/meta-egs/conf/bblayers.conf.sample
deleted file mode 100644
index a7c1dd44d..000000000
--- a/meta-openbmc-mods/meta-egs/conf/bblayers.conf.sample
+++ /dev/null
@@ -1,25 +0,0 @@
-# LAYER_CONF_VERSION is increased each time build/conf/bblayers.conf
-# changes incompatibly
-LCONF_VERSION = "11"
-
-BBPATH = "${TOPDIR}"
-BBFILES ?= ""
-
-BBLAYERS ?= " \
-  ##OEROOT##/meta \
-  ##OEROOT##/meta-poky \
-  ##OEROOT##/meta-openembedded/meta-oe \
-  ##OEROOT##/meta-openembedded/meta-networking \
-  ##OEROOT##/meta-openembedded/meta-perl \
-  ##OEROOT##/meta-openembedded/meta-python \
-  ##OEROOT##/meta-phosphor \
-  ##OEROOT##/meta-aspeed \
-  ##OEROOT##/meta-x86 \
-  ##OEROOT##/meta-openbmc-mods \
-  ##OEROOT##/meta-intel \
-  ##OEROOT##/meta-openbmc-mods/meta-common \
-  ##OEROOT##/meta-openbmc-mods/meta-common-small \
-  ##OEROOT##/meta-openbmc-mods/meta-ast2600 \
-  ##OEROOT##/meta-openbmc-mods/meta-egs \
-  ##OEROOT##/meta-security \
-  "
diff --git a/meta-openbmc-mods/meta-egs/conf/conf-notes.txt b/meta-openbmc-mods/meta-egs/conf/conf-notes.txt
deleted file mode 100644
index 91059a72d..000000000
--- a/meta-openbmc-mods/meta-egs/conf/conf-notes.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Common targets are:
-    intel-platforms
-    obmc-phosphor-image
-    qemu-helper-native
-    virtual/kernel
-    phosphor-ipmi-host
diff --git a/meta-openbmc-mods/meta-egs/conf/layer.conf b/meta-openbmc-mods/meta-egs/conf/layer.conf
deleted file mode 100644
index e139b7249..000000000
--- a/meta-openbmc-mods/meta-egs/conf/layer.conf
+++ /dev/null
@@ -1,14 +0,0 @@
-LOCALCONF_VERSION = "4"
-# We have a conf and classes directory, add to BBPATH
-BBPATH .= ":${LAYERDIR}"
-
-# We have recipes-* directories, add to BBFILES
-BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
-            ${LAYERDIR}/recipes-*/*/*.bbappend"
-
-BBFILE_COLLECTIONS += "egs"
-BBFILE_PATTERN_egs = ""
-BBFILE_PRIORITY_egs = "7"
-LAYERSERIES_COMPAT_egs = "warrior zeus"
-
-PRODUCT_GENERATION = "egs"
diff --git a/meta-openbmc-mods/meta-egs/conf/local.conf.sample b/meta-openbmc-mods/meta-egs/conf/local.conf.sample
deleted file mode 100644
index 369a6f0e1..000000000
--- a/meta-openbmc-mods/meta-egs/conf/local.conf.sample
+++ /dev/null
@@ -1,31 +0,0 @@
-MACHINE ??= "intel-ast2600"
-DISTRO ?= "openbmc-phosphor"
-PACKAGE_CLASSES ?= "package_rpm"
-SANITY_TESTED_DISTROS_append ?= " RedHatEnterpriseWorkstation-6.*"
-EXTRA_IMAGE_FEATURES = "validation-unsecure"
-# Uncomment the following line to enable debug features / default user account.
-#EXTRA_IMAGE_FEATURES += "debug-tweaks"
-USER_CLASSES ?= "buildstats image-mklibs image-prelink"
-PATCHRESOLVE = "noop"
-
-# PFR image Build
-# Before exporting the conf, please uncomment the below line
-# for building Intel PFR compliant images.
-#IMAGE_FSTYPES += "intel-pfr"
-
-BB_DISKMON_DIRS = "\
-    STOPTASKS,${TMPDIR},1G,100K \
-    STOPTASKS,${DL_DIR},1G,100K \
-    STOPTASKS,${SSTATE_DIR},1G,100K \
-    STOPTASKS,/tmp,100M,100K \
-    ABORT,${TMPDIR},100M,1K \
-    ABORT,${DL_DIR},100M,1K \
-    ABORT,${SSTATE_DIR},100M,1K \
-    ABORT,/tmp,10M,1K"
-CONF_VERSION = "4"
-#BB_NUMBER_THREADS = "70"
-
-FULL_OPTIMIZATION = "-Os -pipe ${DEBUG_FLAGS}"
-require conf/distro/include/security_flags.inc
-#SSTATE_DIR="~/.yocto/sstate"
-#DL_DIR="~/.yocto/download"
diff --git a/meta-openbmc-mods/meta-egs/conf/machine/intel-ast2600.conf b/meta-openbmc-mods/meta-egs/conf/machine/intel-ast2600.conf
deleted file mode 100644
index c46d87dde..000000000
--- a/meta-openbmc-mods/meta-egs/conf/machine/intel-ast2600.conf
+++ /dev/null
@@ -1 +0,0 @@
-require conf/machine/include/intel-ast2600.inc
diff --git a/meta-openbmc-mods/meta-wht/conf/local.conf.sample b/meta-openbmc-mods/meta-wht/conf/local.conf.sample
index e5c860f60..7d53790cf 100644
--- a/meta-openbmc-mods/meta-wht/conf/local.conf.sample
+++ b/meta-openbmc-mods/meta-wht/conf/local.conf.sample
@@ -29,3 +29,4 @@ CONF_VERSION = "5"
 
 FULL_OPTIMIZATION = "-Os -pipe ${DEBUG_FLAGS}"
 require conf/distro/include/security_flags.inc
+