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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
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beaglev_fedora_devel
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fedora-vic-7100_5.10.6
master
openwrt-6.1.y
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starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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author
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range
path:
root
/
drivers
/
cxl
/
cxl.h
Age
Commit message (
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)
Author
Files
Lines
2022-08-05
cxl/region: describe targets and nr_targets members of cxl_region_params
Bagas Sanjaya
1
-0
/
+2
2022-08-02
cxl/acpi: Minimize granularity for x1 interleaves
Dan Williams
1
-0
/
+2
2022-08-01
cxl/region: prevent underflow in ways_to_cxl()
Dan Carpenter
1
-1
/
+1
2022-07-26
cxl/region: Introduce cxl_pmem_region objects
Dan Williams
1
-1
/
+35
2022-07-26
cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge
Dan Williams
1
-0
/
+1
2022-07-26
cxl/region: Add region driver boiler plate
Dan Williams
1
-0
/
+1
2022-07-25
cxl/hdm: Commit decoder state to hardware
Dan Williams
1
-1
/
+12
2022-07-25
cxl/region: Program target lists
Dan Williams
1
-0
/
+2
2022-07-25
cxl/region: Attach endpoint decoders
Dan Williams
1
-0
/
+20
2022-07-25
cxl/acpi: Add a host-bridge index lookup mechanism
Dan Williams
1
-0
/
+2
2022-07-25
cxl/region: Enable the assignment of endpoint decoders to regions
Dan Williams
1
-0
/
+11
2022-07-25
cxl/region: Allocate HPA capacity to regions
Dan Williams
1
-0
/
+2
2022-07-25
cxl/region: Add interleave geometry attributes
Ben Widawsky
1
-0
/
+33
2022-07-25
cxl/region: Add a 'uuid' attribute
Ben Widawsky
1
-0
/
+25
2022-07-22
cxl/region: Add region creation support
Ben Widawsky
1
-0
/
+18
2022-07-22
cxl/mem: Enumerate port targets before adding endpoints
Dan Williams
1
-0
/
+5
2022-07-22
cxl/port: Move dport tracking to an xarray
Dan Williams
1
-5
/
+7
2022-07-22
cxl/port: Move 'cxl_ep' references to an xarray per port
Dan Williams
1
-3
/
+1
2022-07-22
cxl/port: Record parent dport when adding ports
Dan Williams
1
-2
/
+5
2022-07-22
cxl/port: Record dport in endpoint references
Dan Williams
1
-0
/
+2
2022-07-22
cxl/hdm: Track next decoder to allocate
Dan Williams
1
-0
/
+2
2022-07-22
cxl/hdm: Add 'mode' attribute to decoder objects
Dan Williams
1
-0
/
+9
2022-07-22
cxl/hdm: Enumerate allocated DPA
Dan Williams
1
-0
/
+2
2022-07-21
cxl/core: Define a 'struct cxl_endpoint_decoder'
Dan Williams
1
-1
/
+14
2022-07-21
cxl/core: Define a 'struct cxl_root_decoder'
Dan Williams
1
-2
/
+13
2022-07-21
cxl/core: Define a 'struct cxl_switch_decoder'
Dan Williams
1
-8
/
+22
2022-07-20
cxl/port: Read CDAT table
Ira Weiny
1
-0
/
+7
2022-07-11
cxl/pmem: Delete unused nvdimm attribute
Dan Williams
1
-1
/
+0
2022-07-10
cxl/port: Cache CXL host bridge data
Dan Williams
1
-0
/
+2
2022-07-10
cxl: Introduce cxl_to_{ways,granularity}
Dan Williams
1
-0
/
+26
2022-07-10
cxl/core: Drop is_cxl_decoder()
Dan Williams
1
-1
/
+0
2022-07-10
cxl/core: Drop ->platform_res attribute for root decoders
Dan Williams
1
-5
/
+1
2022-07-10
cxl/core: Rename ->decoder_range ->hpa_range
Dan Williams
1
-2
/
+2
2022-06-22
cxl/core: Use is_endpoint_decoder
Ben Widawsky
1
-0
/
+1
2022-04-29
cxl: Drop cxl_device_lock()
Dan Williams
1
-78
/
+0
2022-02-09
cxl/core/port: Add endpoint decoders
Ben Widawsky
1
-0
/
+1
2022-02-09
cxl/mem: Add the cxl_mem driver
Ben Widawsky
1
-0
/
+6
2022-02-09
cxl/core/port: Add switch port enumeration
Dan Williams
1
-0
/
+19
2022-02-09
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
1
-4
/
+4
2022-02-09
cxl/port: Add a driver for 'struct cxl_port' objects
Ben Widawsky
1
-0
/
+4
2022-02-09
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
1
-6
/
+27
2022-02-09
cxl/core: Generalize dport enumeration in the core
Dan Williams
1
-12
/
+4
2022-02-09
cxl/pmem: Introduce a find_cxl_root() helper
Dan Williams
1
-0
/
+1
2022-02-09
cxl/port: Introduce cxl_port_to_pci_bus()
Dan Williams
1
-0
/
+3
2022-02-09
cxl/core/port: Use dedicated lock for decoder target list
Dan Williams
1
-0
/
+2
2022-02-09
cxl: Prove CXL locking
Dan Williams
1
-0
/
+81
2022-02-09
cxl/core: Track port depth
Ben Widawsky
1
-0
/
+2
2022-02-09
cxl/core/port: Clarify decoder creation
Ben Widawsky
1
-1
/
+15
2022-02-09
cxl/core: Convert decoder range to resource
Ben Widawsky
1
-2
/
+6
2022-02-09
cxl: Introduce module_cxl_driver
Ben Widawsky
1
-0
/
+3
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